Dps# (I/O); Drdy# (I/O); Drdy_C1# (O); Drdy_C2# (O) - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

A.1.27

DPS# (I/O)

The Deferred Phase Enable (DPS#) signal is driven to the bus on the second clock of
the Request Phase on the Ab[3]# pin. DPS# is asserted if a requesting agent supports
transaction completion using the Deferred Phase. A requesting agent that supports the
Deferred Phase will always assert DPS#. A requesting agent that does not support the
Deferred Phase will always deassert DPS#.
A.1.28

DRDY# (I/O)

The Data Ready (DRDY#) signal is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# can be
deasserted to insert idle clocks.
DRDY# is replicated three times to enable partitioning of data paths in the system
agents. This copy of the Data Ready signal (DRDY#) is an input as well as an output.
A.1.29

DRDY_C1# (O)

DRDY# is a copy of the Data Ready signal. This copy of the Data Phase data-ready
signal (DRDY_C1#) is an output only.
A.1.30

DRDY_C2# (O)

DRDY# is a copy of the Data Ready signal. This copy of the Data Phase data-ready
signal (DRDY_C2#) is an output only.
A.1.31

DSZ[1:0]# (I/O)

The Data Size (DSZ[1:0]#) signals are transferred on REQb[4:3]# signals in the
second clock of the Request Phase by the requesting agent. The DSZ[1:0]# signals
define the data transfer capability of the requesting agent. For the processor, DSZ# =
01, always.
A.1.32

EXF[4:0]# (I/O)

The Extended Function (EXF[4:0]#) signals are transferred on the A[7:3]# pins by the
requesting agent during the second clock of the Request Phase. The signals specify any
special functional requirement associated with the transaction based on the requestor
mode or capability. The signals are defined in
Table A-8.

Extended Function Signals

Extended Function
Signal
EXF[4]#
EXF[3]#
EXF[2]#
EXF[1]#
EXF[0]#
98
Signal Name Alias
Reserved Reserved
SPLCK#/FCL# Split Lock / Flush Cache Line
OWN#/CCL# Memory Update Not Needed / Cache Cleanse
DEN# Defer Enable
DPS# Deferred Phase Supported
Dual-Core Intel
Table A-8.
Function
® ®
Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference