Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual page 29

Electrical Specifications
Table 2-19. Power Connector Pinouts (Sheet 2 of 2)
Power Tab VR Pads
The VR shall provide a selectable output voltage controlled via multiple binary weighted
Voltage Identification (VID) inputs. The VID value (high = 1; low = 0) is defined in
Table 2-20. VID pins will be controlled by the processor.
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Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
A10 - N10
A11 - N11
A12 - N12
A13 - N13
A14 - N14
A15 - N15
A16 - N16
A17 - N17
A18 - N18
A19 - N19
A20 - N20
A21 - N21
A22 - N22
A23 - N23
A24 - N24
A25 - N25
A26 - N26
A27 - N27
A28 - N28
A29
B29
C29
D29
K29
L29
M29
N29
A30 - D30
L30 - N30
Description
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcache
GND
Vcache_sense
Gnd_sense
Vcore_sense
Vfixed_sense
GND
Reserved
Reserved
OUTEN
GND
GND
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