Logical Schematic Of Smbus Circuitry - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual
Dual-core intel itanium processor 9000 and 9100 series
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Also See for P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor:
- Datasheet (113 pages)
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Figure 6-1.
Logical Schematic of SMBus Circuitry
10K
10K
SMA0
SMA1
3.3V
SMA2
System Board
NOTE:
1. Actual implementation may vary.
2. For use in general understanding of the architecture.
80
3.3V
10K
10K
V
CC
A0
A1
SC
Processor
Information
A2
SD
ROM
10K
V
CC
A0
SC
A1
SD
Scratch
EEPROM
A2
WP
SMWP
3.3V
Stuffing
Options
Dual-Core Intel
System Management Feature Specifications
Intel
10K
VCC
A0
Thermal
Sensing
A1
Device
ALERT
SMSD
SMSC
THRMALERT#
System Board
®
®
Itanium
Processor 9000 and 9100 Series Datasheet
Itanium
2 Processor
®
®
Core
THERMDA
THERMDC
STBY
SC
SD
3.3V
10K
000668b
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