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Itanium 9110N
Intel Itanium 9110N Manuals
Manuals and User Guides for Intel Itanium 9110N. We have
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Intel Itanium 9110N manual available for free PDF download: Manual
Intel Itanium 9110N Manual (108 pages)
Dual-Core Intel Itanium Processor 9000 and 9100 Series
Brand:
Intel
| Category:
Computer Hardware
| Size: 1.74 MB
Table of Contents
Table of Contents
3
Revision History
8
Product Features
9
1 Introduction
11
Overview
11
Processor Abstraction Layer
11
Mixing Processors of Different Frequencies and Cache Sizes
12
Terminology
12
State of Data
12
Reference Documents
13
2 Electrical Specifications
15
Dual-Core Intel ® Itanium ® Processor 9000 and 9100 Series System Bus
15
System Bus Power Pins
15
System Bus no Connect
15
System Bus Signals
15
Signal Groups
15
Itanium ® Processor System Bus Signal Groups
16
Signal Descriptions
17
Nominal Resistance Values for Tuner1, Tuner2, and Tuner3
17
Package Specifications
18
Signal Specifications
18
Processor Package Specifications
18
AGTL+ Signals DC Specifications
19
Power Good Signal DC Specifications
19
System Bus Clock Differential HSTL DC Specifications
19
TAP Connection DC Specifications
19
Smbus DC Specifications
20
LVTTL Signal DC Specifications
20
System Bus Clock Differential HSTL AC Specifications
20
Generic Clock Waveform
21
Smbus AC Specifications
21
Maximum Ratings
22
SMSC Clock Waveform
22
Itanium ® Processor Absolute Maximum Ratings
22
System Bus Signal Quality Specifications and Measurement Guidelines
23
Overshoot/Undershoot Magnitude
23
System Bus Signal Waveform Exhibiting Overshoot/Undershoot
23
Overshoot/Undershoot Pulse Duration
24
Activity Factor
24
Reading Overshoot/Undershoot Specification Tables
24
Determining if a System Meets the Overshoot/Undershoot Specifications
25
Wired-OR Signals
25
Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group Absolute Overshoot/Undershoot Tolerance
25
Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/Undershoot Tolerance for 400-Mhz System Bus
26
Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot Tolerance for 400-Mhz System Bus
26
Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/Undershoot Tolerance for 533-Mhz System Bus
26
Voltage Regulator Connector Signals
27
Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot Tolerance for 533-Mhz System Bus
27
VR Connector Signals
27
Processors Power Tab Physical Layout
28
Power Connector Pinouts
28
Processors Core Voltage Identification Code (VCORE and VCACHE)
30
System Bus Clock and Processor Clocking
31
System Bus Reset and Configuration Timings for Cold Reset
31
System Bus Reset and Configuration Timings for Warm Reset
32
Recommended Connections for Unused Pins
33
Connection for Unused Pins
33
TUNER1/TUNER3 Translation Table
34
3 Pinout Specifications
35
Dual-Core Intel ® Itanium ® Processor 9000 and 9100 Series Pinout
35
Pin/Signal Information Sorted by Pin Name
36
Pin/Signal Information Sorted by Pin Location
50
4 Mechanical Specifications
65
Processor Package Dimensions
65
Processor Package
66
Package Height and Pin Dimensions
67
Processor Package Dimensions
67
Processor Package Mechanical Interface Dimensions
68
Processor Package Mechanical Interface Dimensions
69
Processor Package Top-Side Components Height Dimensions
70
Processor Package Bottom-Side Components Height Dimensions
70
Voltage Regulator (MVR) to Processor Package Interface
71
Processor to MVR Interface Loads
71
Processor Package Load Limits at Power Tab
71
Package Marking
72
Processor Top-Side Marking
72
Processor Bottom-Side Marking
73
Processor Top-Side Marking on IHS
73
Processor Bottom-Side Marking Placement on Interposer
74
5 Thermal Specifications
75
Thermal Features
75
Thermal Alert
75
Dual-Core Intel ® Itanium ® Processor 9000 and 9100 Series Thermal Features
75
Enhanced Thermal Management
76
Power Trip
76
Thermal Trip
76
Case Temperature
76
Itanium ® Processor Package Thermocouple Location
77
Case Temperature Specification
77
6 System Management Feature Specifications
79
System Management Bus
79
System Management Bus Interface
79
System Management Interface Signals
79
System Management Interface Signal Descriptions
79
Logical Schematic of Smbus Circuitry
80
Smbus Device Addressing
81
Thermal Sensing Device Smbus Addressing on the Dual-Core Intel
81
Processor Information ROM
82
EEPROM Smbus Addressing on the Dual-Core Intel
82
Processor Information ROM Format
82
Scratch EEPROM
85
Processor Information ROM and Scratch EEPROM Supported Smbus Transactions
85
Current Address Read Smbus Packet
85
Thermal Sensing Device
86
Random Address Read Smbus Packet
86
Byte Write Smbus Packet
86
Thermal Sensing Device Supported Smbus Transactions
87
Write Byte Smbus Packet
87
Read Byte Smbus Packet
87
Send Byte Smbus Packet
87
Receive Byte Smbus Packet
87
ARA Smbus Packet
87
Thermal Sensing Device Registers
88
Thermal Reference Registers
88
Command Byte Bit Assignment
88
Thermal Limit Registers
89
Status Register
89
Configuration Register
89
Thermal Sensing Device Status Register
89
Thermal Sensing Device Configuration Register
89
Conversion Rate Register
90
Thermal Sensing Device Conversion Rate Register
90
Signals Reference
91
Alphabetical Signals Reference
91
A[49:3]# (I/O)
91
A20M# (I)
91
Ads# (I/O)
91
Ap[1:0]# (I/O)
91
Asz[1:0]# (I/O)
91
Attr[3:0]# (I/O)
92
Bclkp/Bclkn (I)
92
Be[7:0]# (I/O)
92
Address Space Size
92
Effective Memory Type Signal Encoding
92
Berr# (I/O)
93
Special Transaction Encoding on Byte Enables
93
Binit# (I/O)
94
Bnr# (I/O)
94
Bpm[5:0]# (I/O)
94
Bpri# (I)
94
BR[0]# (I/O) and BR[3:1]# (I)
94
Breq[3:0]# (I/O)
95
BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect
95
BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect
95
BR[3:0]# Signals and Agent Ids
95
Ccl# (I/O)
96
Cpupres# (O)
96
D[127:0]# (I/O)
96
D/C# (I/O)
96
Dbsy# (I/O)
96
Dbsy_C1# (O)
96
Dbsy_C2# (O)
96
Defer# (I)
96
Den# (I/O)
97
Dep[15:0]# (I/O)
97
Dhit# (I)
97
DID[9:0]# Encoding
97
Dps# (I/O)
98
Drdy# (I/O)
98
Drdy_C1# (O)
98
Drdy_C2# (O)
98
Dsz[1:0]# (I/O)
98
Exf[4:0]# (I/O)
98
Itanium ® Processor
98
Extended Function Signals
98
Fcl# (I/O)
99
Ferr# (O)
99
Gseq# (I)
99
HIT# (I/O) and HITM# (I/O)
99
Ids# (I)
99
Ignne# (I)
99
Init# (I)
99
Int (I)
100
Len[2:0]# (I/O)
100
Lint[1:0] (I)
100
Lock# (I/O)
100
Length of Data Transfers
100
Nmi (I)
101
Own# (I/O)
101
Pmi# (I)
101
Pwrgood (I)
101
Req[5:0]# (I/O)
101
Reset# (I)
102
Rp# (I/O)
102
Transaction Types Defined by Reqa#/Reqb# Signals
102
Rsp# (I)
103
Sbsy# (I/O)
103
Sbsy_C1# (O)
103
Sbsy_C2# (O)
103
Splck# (I/O)
103
Stbn[7:0]# and Stbp[7:0]# (I/O)
103
Tck (I)
104
Tdi (I)
104
Tdo (O)
104
Thrmtrip# (O)
104
Thrmalert# (O)
104
Tms (I)
104
Tnd# (I/O)
104
Stbp[7:0]# and Stbn[7:0]# Associations
104
Trdy# (I)
105
Trst# (I)
105
Wsnp# (I/O)
105
Signal Summaries
105
Output Signals
105
Input Signals
105
Input/Output Signals (Single Driver)
106
Input/Output Signals (Multiple Driver)
107
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