Electrical Specifications; Dual-Core Intel ® Itanium ® Processor 9000 And 9100 Series System Bus; System Bus Power Pins; System Bus No Connect - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Electrical Specifications

2
Electrical Specifications
This chapter describes the electrical specifications of the Dual-Core Intel Itanium
Processor 9000 and 9100 series.
2.1 Dual-Core Intel
9100 Series System Bus
Most Dual-Core Intel Itanium processor 9000 and 9100 series signals use the Itanium
processor's assisted gunning transceiver logic (AGTL+) signaling technology. The
termination voltage, V
reference voltage. The buffers that drive most of the system bus signals on the
processor are actively driven to V
times and reduce noise. These signals should still be considered open-drain and require
termination to V
terminated to V
termination, in which case, the termination is provided by external resistors connected
to V
CTERM
AGTL+ inputs use differential receivers which require a reference signal (V
used by the receivers to determine if a signal is a logical 0 or a logical 1. The processor
generates V
source.
2.1.1

System Bus Power Pins

VCTERM (1.2 V) input pins on the processor provide power to the driver buffers and on-
die termination. The GND pins, in addition to the GND input at the power tab connector,
provide ground to the processor. Power for the processor core is supplied through the
power tab connector by V
to provide power to the system management bus (SMBus). The V
pins must remain electrically separated from each other.
2.1.2

System Bus No Connect

All pins designated as "N/C" or "No Connect" must remain unconnected.
2.2

System Bus Signals

2.2.1

Signal Groups

Table 2-1
buffer type and whether they are inputs, outputs, or bidirectional, with respect to the
processor.
® ®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
®
Itanium
, is generated on the baseboard and is the system bus high
CTERM
which provides the high level. The processor system bus is
CTERM
at each end of the bus. There is also support of off-die
CTERM
.
on-die, thereby eliminating the need for an off-chip reference voltage
REF
, V
Core Cache,
shows processor system bus signals that have been combined into groups by
®
Processor 9000 and
during a low-to-high transition to improve rise
CTERM
V The 3.3 V pin is included on the processor
fixed.
). V is
REF REF
, 3.3 V, and GND
CTERM
15