Electrical Specifications
Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2)
Symbol
Parameter
T
BCLKp Rise Time
rise
T
BCLKp Fall Time
fall
V
Minimum Input Swing
PP
Notes:
1. The system clock skew is ±100 ps.
2. Measured on cross-point of rising edge of BCLKp and falling edge of BCLKn. Long-term jitter is defined as peak-to-peak variation
measured by accumulating a large number of clock cycles and recording peak-to-peak jitter.
3. Cycle-to-cycle jitter is defined as peak-to-peak variation measured over 10,000 cycles peak-to-peak jitter.
4. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn.
5. The system clock skew is ±60 ps.
6. V
is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
PPmin
7. The measurement is taken at 40-60% of the signal and extrapolated to 20-80%.
Table 2-11. SMBus AC Specifications
Symbol
f
SMSC
T
SMSC
t
high
t
low
t
rise
t
fall
t
VALID
t
SU
t
HLD
t
FREE
Notes:
1. Please refer to
2. Bus Free Time is the minimum time allowed between request cycles.
Figure 2-1.
Generic Clock Waveform
V
pp
®
®
Dual-Core Intel
Itanium
Processor 9000 and 9100 Series Datasheet
System
Bus
Minimum
Clock
(MHz)
7
All
7
All
All
Parameter
SMSC Clock Frequency
SMSC Clock Period
SMSC Clock High Time
SMSC Clock Low Time
SMSC Clock Rise Time
SMSC Clock Fall Time
SMBus Output Valid Delay
SMBus Input Setup Time
SMBus Input Hold Time
Bus Free Time
Figure 2-2
for the Standard Microsystems Corporation (SMSC)* clock waveform.
T
high
T
rise
80%
20%
T
period
T
T
=
Rise Time
period
rise
T
T
=
Fall Time
fall
jitter
V
T
=
High Time
pp
high
T
=
Low Time
low
Typ
Maximum
333
500
667
333
500
667
600
Minimum
10
4.0
4.7
250
0
4.7
T
low
T
BCLKN
fall
BCLKP
=
=
Period
=
Long Term Peak-to-Peak Jitter
=
Peak-to-Peak Swing
Unit
Figure
Notes
ps
Figure 2-1
20–80%
ps
Figure 2-1
20–80%
6
mV
Figure 2-1
Maximum
Unit
Notes
100
kHz
µs
1
µs
1
µs
1
1.0
µs
1
0.3
µs
1.0
µs
ns
ns
2
µs
T
jitter
000615
21
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