Introduction; Overview; Processor Abstraction Layer - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Introduction

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Introduction
1.1

Overview

The Dual-Core Intel Itanium processor 9000 and 9100 series employs Explicitly Parallel
Instruction Computing (EPIC) design concepts for a tighter coupling between hardware
and software. In this design style, the interface between hardware and software is
engineered to enable the software to exploit all available compile-time information and
efficiently deliver this information to the hardware. It addresses several fundamental
performance bottlenecks in modern computers, such as memory latency, memory
address disambiguation, and control flow dependencies. The EPIC constructs provide
powerful architectural semantics and enable the software to make global optimizations
across a large scheduling scope, thereby exposing available Instruction Level
Parallelism (ILP) to the hardware. The hardware takes advantage of this enhanced ILP,
and provides abundant execution resources. Additionally, it focuses on dynamic run-
time optimizations to enable the compiled code schedule to flow at high throughput.
This strategy increases the synergy between hardware and software, and leads to
greater overall performance.
The Dual-Core Intel Itanium processor 9000 and 9100 series provides a 6-wide and 8-
stage deep pipeline, running at up to 1.6 GHz. This provides a combination of abundant
resources to exploit ILP as well as increased frequency for minimizing the latency of
each instruction. The resources consist of six integer units, six multimedia units, two
load and two store units, three branch units, two extended-precision floating-point
units, and one additional single-precision floating-point unit per core. The hardware
employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking
caches to optimize for compile-time non-determinism. Three levels of on-die cache
minimize overall memory latency. This includes up to a 24 MB L3 cache, accessed at
core speed, providing up to 8.53 GB/sec. of data bandwidth. The system bus is
designed to support up to four physical processors (on a single system bus), and can
be used as an effective building block for very large systems. The balanced core and
memory subsystem provide high performance for a wide range of applications ranging
from commercial workloads to high-performance technical computing.
The Dual-Core Intel Itanium processor 9000 and 9100 series supports a range of
computing needs and configurations from a two-way to large SMP servers. This
document provides the electrical, mechanical and thermal specifications for the Dual-
Core Intel Itanium processor 9000 and 9100 series for use while employing systems
with the processors.
1.2

Processor Abstraction Layer

The Dual-Core Intel Itanium processor 9000 and 9100 series requires implementation-
specific Processor Abstraction Layer (PAL) firmware. PAL firmware supports processor
initialization, error recovery, and other functionality. It provides a consistent interface
to system firmware and operating systems across processor hardware
implementations. The Intel
Volume 2: System Architecture, describes PAL. Platforms must provide access to the
firmware address space and PAL at reset to allow the processors to initialize.
® ®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
® ®
Itanium Architecture Software Developer's Manual,
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