Table of Contents
Advertisement
Technologies, Inc.
We Connect
We Connect
Signal Name
HCLK
DCLKO
DCLKWR
GCLKO
GCLK
PCLK
RESET#
PWROK
GCKRUN# / GPAR
SUSCLK
SUSTAT#
CPURSTI#
CLKRUN#
Signal Name
VCC
GND
VCCA
GNDA
VSUS
VCCQ
VCCQQ
GNDQQ
VTT
GTLREF
AGPREF
TESTIN#
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
CLOCK AND RESET CONTROL
I/O
I
Connect to the CPU clock output of the system clock synthesizer.
O
Connect to the SDRAM clock input of the system clock synthesizer.
I
Connect to the SDRAM clock output of the system clock synthesizer.
O
Connected to the AGP clock input of the AGP slot through a 22 ohm resistor.
I
Connected to the GCLKO of VT82C694X through a 22 ohm resistor.
I
Connect to the PCI clock output of the system clock synthesizer.
I
Connected to VT82C686A through a 74F240 inverter.
I
Connect to VT82C686A and Power Good circuitry.
O/IO Connected to VT82C686A and the system clock synthesizer if the function is applied.
I
Connect to VT82C686A. 10K ohm pull-up to VCC3.
I
Connect to VT82C686A. 10K ohm pull-up to VCC3.
I
Connect to the MUX circuitry of the CPU strapping signals. 10K ohm pull-up to VCC3.
I
Connected to VT82C686A and the system clock synthesizer if the function is applied.
Otherwise, connect to VT82C686A then through a 100 ohm serial resistor to ground.
MISCELLANEOUS
I/O
P
Connect to VCC3.
P
Connect to ground.
P
Connect to VCC3.
P
Connect to ground.
P
Connect to 3.3V standby power source.
P
Connect to VDDQ (1.5V or 3.3V).
P
Connect to VDDQ (1.5V or 3.3V).
P
Connect to ground.
P
Connect to GTL threshold voltage (1.5V).
P
Connect to GTL Buffer reference voltage (1.0V) circuitry.
P
Connect to AGP reference voltage (1.32V) circuitry.
I
8.2K ohm pull-up to VCC3.
Connection
Connection
80
Signal Connectivity and Design Checklist
Advertisement
Table of Contents
