Figure 2-50. Agp 4X Interface Layout Example - VIA Technologies Apollo Pro133A Design Manual

Technologies, Inc.
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
We Connect We Connect
(b) Solder Side

Figure 2-50. AGP 4X Interface Layout Example

Notes:
1. Most Decoupling capacitors are placed on the left-hand side of the AGP slot in Figure 2-50 (a).
2. Discrete pull-up resistors are located very near their associated pins for the short stub limitation in Figure 2-50 (a).
3. Each Strobe signal is centered within its group to minimize the signal to strobe skew.
4. The serpentine bold trace near the VT82C694X chip represents the AGP clock feedback (GCLKI) signal in Figure 2-50 (b).
5. There are five SMD ceramic capacitors located in the inner AGP quadrant of BGA area in Figure 2-50 (b).
6. In order to prevent couplings from or to other signal groups (e.g. PCI), a surrounding ground plane is applied near the AGP
universal (2X or 4X) slot on either the component layer or the solder layer.
Preliminary Revision 0.5, November 19, 1999 57 Motherboard Design Guidelines