Apollo Pro133A Clock Layout Recommendations; Clock Requirements; Figure 2-21. System Clock Connections; Table 2-7. Apollo Pro133A Clock Synthesizer Requirements - VIA Technologies Apollo Pro133A Design Manual

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2.3.2 Apollo Pro133A Clock Layout Recommendations

2.3.2.1 Clock Requirements

The requirements of the system clock synthesizer for an Apollo Pro133A based system design are listed in Table 2-7.
Clock Signal Type
CPU Clock
SDRAM Clock
SDRAM Clock In
PCI Clock
USB Clock
Super I/O Clock
IOAPIC Clock
Reference Clock
Note: The voltage level for CPU and IOAPIC clock signals is 2.5V. The voltage level for the remaining clocks is 3.3V.
Figure 2-21 shows clock connections of the system clock synthesizers to their respective destinations.
Preliminary Revision 0.5, November 19, 1999

Table 2-7. Apollo Pro133A Clock Synthesizer Requirements

Frequency (MHz) Quantity
66/75/83/95/ 3
100/124/133
66/100/133 17
66/100/133 1
33 7
48 1
24 1
14.31818 1
14.31818 2
P
C
PCLK (5)
I
PCICLK(1)
USBCLK
VT82C686A
Reference CLK
I Reference CLK
S
A

Figure 2-21. System Clock Connections

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Connect to CPU (1), Apollo Pro133A (1) and ITP Debug Port (1)
Connect to four SDRAM slots (16) and Apollo Pro133A (1)
Connect to Apollo Pro133A (1)
Connect to Apollo Pro133A (1), South Bridge (1), and PCI slots (5)
Connect to South Bridge (1)
Connect to Super I/O (1) if an external Super I/O is used
Connect to Slot-1 or Socket-370 CPU
Connect to South Bridge (1) and ISA slots (1)
IOAPIC CLK
CPUCLK
CPUCLK(1)
System
SDCLK
Clock
DCLKO
Synthesizer
PCICLK(1)
Super I/O CLK
SDCLK[16:0]
30
Connections
Slot-1 or
Socket-370
CPU
VT82C694X
Super I/O
(If used)
DIMM
Motherboard Design Guidelines