VIA Technologies Apollo Pro133A Manuals

Manuals and User Guides for VIA Technologies Apollo Pro133A. We have 1 VIA Technologies Apollo Pro133A manual available for free PDF download: Design Manual

VIA Technologies Apollo Pro133A Design Manual (140 pages)

Brand: VIA Technologies | Category: Network Hardware | Size: 2.6 MB

Revision History
3
Table of Contents
4
Table of Contents
5
List of Figures
7
Introduction
11
About this Design Guide
11
Apollo Pro133A Chipset Overview
12
VT82C694X Apollo Pro133A North Bridge Features
12
Super South (VT82C686A) Chipset Features
13
System Block Diagram
14
Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge
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System Design Recommendations
15
Motherboard Design Guidelines
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Ballout Assignment
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Apollo Pro133A North Bridge Ballout Assignment
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Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View)
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Super South" South Bridge Ballout Assignment
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Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View)
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Motherboard Description
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Slot-1 Motherboard Placement and Routing
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Table 2-1. Different Board Size Lists for Slot-1 System
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ATX Form Factor for Slot-1 System
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Figure 2-3. ATX Placement and Routing Example for Slot-1 System
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Micro ATX Form Factor for Slot-1 System
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Figure 2-4. Micro-ATX Placement and Routing Example for Slot-1 System
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Socket-370 Motherboard Placement and Routing
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Table 2-2. Different Board Size Lists for Socket-370 System
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ATX Form Factor for Socket-370 System
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Figure 2-5. ATX Placement and Routing Example for Socket-370 System
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Micro ATX Form Factor for Socket-370 System
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Figure 2-6. Micro-ATX Placement and Routing Example for Socket-370 System
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Printed Circuit Board Description
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Four-Layer Board
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Figure 2-7. Four-Layer Stack-Up with 2 Signal Layers and 2 Power Planes
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Six-Layer Board
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Figure 2-8. Six-Layer Stack-Up with 4 Signal Layers and 2 Power Planes
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On Board Power Regulation
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Capacitive Decoupling
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Figure 2-9. Example of Via Location
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Single Slot-1 Processor Capacitive Decoupling
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Figure 2-10. Decoupling Capacitor Placement for Single Slot-1 Processor
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Single Socket-370 Processor Capacitive Decoupling
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Figure 2-11. Decoupling Capacitor Placement for Single Socket-370 Processor
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Table 2-3. High Frequency and Bulk Decoupling Capacitor Distribution Around Socket-370
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Apollo Pro133A Chipset Capacitive Decoupling
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DRAM Module Capacitive Decoupling
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Figure 2-12. Decoupling Capacitor Placements for VT82C694X and VT82C686A
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Figure 2-13. Decoupling Capacitor Placements for DRAM Modules
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Power Plane Partitions
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Power Plane Partitions for Slot-1 Motherboard
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Figure 2-14. ATX Power Plane Partitions for Slot-1 System
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Figure 2-15. Micro-ATX Power Plane Partitions for Slot-1 System
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Power Plane Partitions for Socket-370 Motherboard
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Figure 2-16. ATX Power Plane Partitions for Socket-370 System
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Figure 2-17. Micro-ATX Power Plane Partitions for Socket-370 System
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Chipset Power and Ground Layout Recommendations
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Figure 2-18. VT82C694X Power and Ground Layout
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Figure 2-19. VT82C686A Power and Ground Layout
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Power up Configuration
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Figure 2-20. a Typical Example of a 3-Pin Jumper Strapping Circuit
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VT82C694X Power up Strappings
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VT82C686A Power up Strappings
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Table 2-4. Power-Up Configuration for VT82C694X
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Table 2-5. Power-Up Configuration for VT82C686A
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General Layout and Routing Guidelines
39
Trace Attribute Recommendations
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Table 2-6. Recommended Trace Width and Spacing
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Apollo Pro133A Clock Layout Recommendations
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Clock Requirements
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Figure 2-21. System Clock Connections
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Table 2-7. Apollo Pro133A Clock Synthesizer Requirements
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Clocking Scheme
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Figure 2-22. Apollo Pro133A Chip Clocking Scheme
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Clock Routing Considerations
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Figure 2-23. Clock Trace Spacing Guidelines
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Figure 2-24. Effect of Ground Plane to a Clock Signal
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Figure 2-25. Series Termination for Multiple Clock Loads
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System Clock Combinations
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Table 2-8. Apollo Pro133A System Clock Combinations
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Host CPU Clock and SDRAM Clock Signals
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Figure 2-26. Host Clock and SDRAM Clock Layout Recommendations for Slot-1 System
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Figure 2-27. Host Clock and SDRAM Clock Layout Recommendations for Socket-370 Systems
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AGP Clock Signals
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Figure 2-28. AGP Clock Layout Recommendations
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PCI Clock Signals
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Miscellaneous Clock Signals
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Figure 2-29. PCI Clock Layout Recommendations
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Clock Trace Length Calculation
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Routing Styles and Topology
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Figure 2-30. Daisy Chain Routing Example
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Figure 2-31. Point-To-Point and Multi-Drop Topology Examples
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Figure 2-32. Alternate Multi-Drop Topology Example
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VT82C694X Apollo Pro133A Layout and Routing Guidelines
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Host CPU Interface Layout and Routing Guidelines
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Slot-1 Host Interface to North Bridge
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Figure 2-33. Slot-1 Host Interface Topology Example
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Socket-370 Host Interface to North Bridge
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Figure 2-34. Socket-370 Host Interface Topology Example
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Figure 2-35. Host Interface Layout Example between Socket-370 and VT82C694X
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CPU Host Interface to South Bridge
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Figure 2-36. Schematic Example for Slot-1 CPU Internal/External Clock Ratio Pin Sharing
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Table 2-9. Host Control Signals to South Bridge
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Figure 2-37. Layout Example of Control Signal from South Bridge to Slot-1 CPU
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Figure 2-38. Layout Example of Control Signal from South Bridge to Socket-370 CPU
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Memory Subsystem Layout and Routing Guidelines
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DRAM Routing Guidelines
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Table 2-10. Memory Subsystem Signals
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Figure 2-39. Daisy Chain Routing for Four-DRAM DIMM Slots
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Figure 2-40. Daisy Chain Routing for Three-DRAM DIMM Slots
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Figure 2-41. T-Style Routing for Three-DRAM DIMM Slots
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DRAM Reference Layout
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Figure 2-42. Daisy Chain Routing for Two-DRAM DIMM Slots
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Figure 2-43. DRAM Placement for 133Mhz Timing Consideration
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Figure 2-44. Layout Example of Three-DRAM DIMM Slots
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AGP (4X Mode) Interface Layout and Routing Guidelines
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General Layout and Routing Recommendations
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Figure 2-45. General Layout Recommendations of AGP 4X Interface
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Table 2-11. VT82C694X AGP 4X Signal Groups
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Vref Characteristics for AGP 4X Mode
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AGP VDDQ Power Delivery
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Figure 2-46. AGP 2X and 4X Mode Sharing Circuit
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Figure 2-47. VDDQ Voltage-Switching Application Circuit
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Figure 2-48. VDDQ Voltage-Switching Application Circuit (II)
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AGP VDDQ Power Plane Partition
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Figure 2-49. AGP VDDQ Power Plane Partition Example
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Optimized Layout and Routing Recommendations
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Figure 2-50. AGP 4X Interface Layout Example
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PCI Interface Layout and Routing Guidelines
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Figure 2-51. Topology Example of AGP and PCI Interface
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Super South (VT82C686A) Layout and Routing Guidelines
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USB Controller
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Figure 2-52. USB Over-Current Scan Logic
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Table 2-12 Universal Serial Bus (USB) Signals
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Figure 2-53. USB Differential Signal Routing Example
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AC'97 Link and Game/MIDI Ports
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AC'97 Link
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Table 2-13. Signal Description of AC'97 Link and Game/MIDI Ports
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Game/MIDI Ports
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Figure 2-54. AC'97 Link Example
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Figure 2-55. MIDI/Game Port Application Circuit
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Hardware Monitoring
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Figure 2-56. Hardware Monitoring Application Circuit
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Integrated Super IO Controller
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System Management Bus Interface
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Figure 2-57. System Management Bus Interface
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Ide
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Figure 2-58. ISA Bus SA[15:0] / SDD[15:0] Sharing Circuitry
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Figure 2-59. IDE Interfaces Layout Guidelines
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Figure 2-60. Ultra DMA/66 Placement and Routing Example
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Figure 2-61. Ultra DMA/66 Application Circuit
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Suspend to DRM
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Suspend DRAM Refresh
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Figure 2-62. Suspend DRAM Refresh Application Circuit
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STR Power Plane Control
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Figure 2-63. STR State Power Plane Control Application Circuit
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Table 2-14. Resume Events Supported in Different Power States
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Timing Analysis and Simulation
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SDRAM Timing
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Figure 3-1. CPU Read from SDRAM (SL=2)
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Figure 3-2. CPU Post Write to SDRAM (SL=2)
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Electrical Specifications
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Absolute Maximum Ratings
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Recommended Operating Ranges
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Table 4-1. Absolute Maximum Ratings
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Table 4-2. Recommended Operating Ranges
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DC Characteristics
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Power Dissipation
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Table 4-3. DC Characteristics
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Table 4-4. Maximum Power Dissipation
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Signal Connectivity and Design Checklist
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Overview
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VT82C694X Apollo Pro133A North Bridge
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Table 5-1. VT82C694X North Bridge Connectivity
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Super South" South Bridge Controller
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Table 5-2. VT82C686A South Bridge Connectivity
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Apollo Pro-133A Design Checklist
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General Layout Considerations Checklist
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Major Components Checklist
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Table 5-3. Recommended Trace Width and Spacing
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Decoupling Recommendations Checklist
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Clock Trace Checklist
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Clock Trace Length Calculation
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Signal Trace Attribute Checklist
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Table 5-4. Maximum Accumulated Trace Length
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Appendices
105
Appendix A - SPKR Strapping Application Circuits
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Figure A-1. VT82C686A SPKR Pin Transistor Driver Solution (I)
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Figure A-2. VT82C686A SPKR Pin Inverter Driver Solution (II)
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Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines
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Introduction
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Figure B-1. AC'97 Audio Codec and Game/MIDI Port Block Diagram
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Layout Recommendations
110
Component Placement
110
Figure B-2. AC'97 Audio Codec and GAME/MIDI Port Placement Example
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Table B-1. Decoupling Capacitor List
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Table B-2. AC-Coupling Capacitors for Audio Input Signals
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Table B-3. AC-Coupling Capacitors for Audio Input Signals
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Ground and Power Planes
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Figure B-3. Ground Layer Layout Example
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Figure B-4. Power Layer Layout Example
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Table B-4. Signal Groups Associated with Their Audio Ground Plane
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Routing Guidelines
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Figure B-5. Component Layer Layout Example
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Figure B-6. Solder Layer Layout Example
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Table B-5. Routing Guidelines for Signal Nets
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Table B-6. Routing Guidelines for Power and Ground Nets
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Appendix C - Apollo Pro133A Reference Design Schematics
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Figure C-1. Apollo Pro133A Reference Component Placement
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