Clocking Scheme; Figure 2-22. Apollo Pro133A Chip Clocking Scheme - VIA Technologies Apollo Pro133A Design Manual

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2.3.2.2 Clocking Scheme

The 17 (66 / 100 / 133MHz) SDRAM clocks are generated from a clock buffer inside the system clock synthesizer. They are
controlled by the SDRAM clock output (DCLKO) provided by the Apollo Pro133A North Bridge. The VT82C694X (North
Bridge) has a built-in de-skew Phase Lock Loop (PLL) circuitry for optimal skew control within and between clocking regions.
For more details, refer to Figure 2-22.
Clock
Synthesizers
VT82C694X (North Bridge)
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
CCLK
DRAM Clock
DCLK
De-skew PLL
AGP Clock
GCLK
De-skew PLL
GCLK4XI

Figure 2-22. Apollo Pro133A Chip Clocking Scheme

31
HCLK
External Clock
Synthesizer
with SDRAM
Clock Buffer
DCLK
DCLKO
DCLKI
GCLK
22 ohm
GCLKO
22 ohm
GCLKI
HCLK: External Host clock - 66MHz / 100MHz / 133MHz
CCLK: Internal Host clock - 66MHz / 100MHz / 133MHz
DCLK: Memory (SDRAM) clock - 66MHz / 100MHz / 133MHz
GCLK: AGP clock - 66MHz only
GCLK4XI: AGP 4X clock - 266MHz
4 SDCLKs to
each DIMM
GCLKO
to AGP slot
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