Figure 2-27. Host Clock And Sdram Clock Layout Recommendations For Socket-370 Systems - VIA Technologies Apollo Pro133A Design Manual

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We Connect We Connect
CPUCLK
SDCLKIN
SDCLK_F
System
Clock
Synthesizer
SDCLK0
SDCLK1
SDCLK2
SDCLK3
SDCLK4
SDCLK5
SDCLK6
SDCLK7
SDCLK8
SDCLK9
SDCLK10
SDCLK11
SDCLK12
SDCLK13
SDCLK14
SDCLK15

Figure 2-27. Host Clock and SDRAM Clock Layout Recommendations for Socket-370 Systems

Preliminary Revision 0.5, November 19, 1999
0 ~ 33
10 ~ 33 pF
ohm
HCLK
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
L
NB
L
NB
L
DOUT
(as short as possible)
L + 4.5"
SD
L
SD
L
SD
L
SD
L
SD
35
Socket-370
CPU
VT82C694X
HCLK
0 ~ 33
ohm
DCLKO
10 ~ 33 pF
(near the chip)
DCLKWR
10 ~ 33 pF
(near the chip)
DIMM1
CK0
CK1
CK2
CK3
DIMM2
CK0
CK1
CK2
CK3
DIMM3
CK0
CK1
CK2
CK3
DIMM4
CK0
CK1
CK2
CK3
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