Signal Trace Attribute Checklist; Table 5-4. Maximum Accumulated Trace Length - VIA Technologies Apollo Pro133A Design Manual

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5.4.6 Signal Trace Attribute Checklist

The maximum accumulated trace length as a brief layout reference for high-speed or critical signal groups (e.g. host and memory)
is listed in Table 5-4. The accumulated trace length represents the total trace length or the length sum of two traces before and
after a damping resistor. It is recommended to route the same signal groups in equal length and as short as possible. A minimum
of 5 mils in width and a minimum of 10 mils in spacing are required for all these signals.
Host Address
Host Data
Host Control
Host Compatibility (from VT82C686A)
Memory Address
Memory Data
Memory Control
AGP Address / Data
AGP Strobe
AGP Control
PCI Address / Data
PCI Control
USB Data
System Management Bus
IDE Data
IDE Control
Notes:
1. When using Socket-370 CPU, VTT termination stub for the host interface should be less than 2". Both the VTT termination stub
and the trace connected to VT82C694X (NB) directly come out the pin of the Socket-370. The location of these termination (56
ohm) resistor networks should be placed as close to Socket-370 CPU as possible. No VTT termination is needed for a Slot-1
CPU based system.
2. Each VT82C686A south bridge Open Drain (OD) output control signal to the CPU needs a 150 ~ 450 ohm pull-up which should
be placed as close to the VT82C686A chip as possible.
3. The trace width of six strobe lines (GDS[1:0], GDS[1:0]#, SBS and SBS#) is 5 mils. Trace length mismatch in any Data/Strobe
group should be maintained within 0.5 inch. The maximum pull-up stub trace length on strobe lines and other traces should be
less than 0.5 inch. Instead of R-packs, discrete pull-up resistors should be used. It is strongly recommended to keep the stub
length as short as possible and maintain the trace length of all AGP (especially Data and Strobe) signals less than 6 inches. It
is always best to reduce line mismatch to add to the timing margin. In other words, a balanced topology will match trace
lengths within the groups to minimize skew. To minimize signal crosstalk, wider spacing is recommended wherever possible
between traces.
4. The VT82C694X and VT82C686A should be placed at both ends of the PCI bus for better signal termination.
5. Each pair of USB data signals is required to be parallel to each other with the same trace length. Each pair of USB data
signals is required to be parallel to a relative ground plane.
6. Adding 68pF capacitors to the system management bus at the end device is essential since the I2C bus travels a long way and
might pick up noise along the route.
7. All signals for primary IDE and Secondary IDE require 33 ohm series termination resistors. These series terminations should
be placed as close as possible (less than 1 inch) to the VT82C686A. Data and strobe lines (DD[15..0], IOR#, IOW#, and
IORDY#) should be routed as a bus. The total trace length of these signals should be shorter than 4.5 inches. The maximum
trace length difference among them must be less than 1 inch. Other lines should be as short as possible. Signal DD7 needs a
10K pull-down on the VT82C686A chip side of the series termination. Signal DREQ needs a 5.6K pull-down on the connector
side of the series termination. Signal IRQ14 (and IRQ15) needs a 10K pull-down or pull-up (preferred) on the connector side of
the series termination. Signal IORDY# needs a 1K pull-up on the connector side of the series termination. Pin 28 of the IDE
connectors should be tied to ground with a 470 ohm serial resistor.
Preliminary Revision 0.5, November 19, 1999

Table 5-4. Maximum Accumulated Trace Length

Signal Group
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Maximum accumulated trace length
4.5"
4.5"
4.5"
As short as possible.
4"
4"
6"
6"
6"
6"
As short as possible.
As short as possible.
As short as possible.
As short as possible.
4.5"
4.5"
94
Note
1
1
1
2
3
3
3
4
4
5
6
7
7
Signal Connectivity and Design Checklist