Cpu Host Interface To South Bridge; Figure 2-36. Schematic Example For Slot-1 Cpu Internal/External Clock Ratio Pin Sharing; Table 2-9. Host Control Signals To South Bridge - VIA Technologies Apollo Pro133A Design Manual

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2.4.1.3 CPU Host Interface to South Bridge

The host control signals from the Slot-1 or Socket-370 CPU to the south bridge (VT82C686A) are listed in Table 2-9. Except for
FERR#, all signals are open drain (OD). 2.5V pull-ups are required for those open drain signals on the VT82C686A chip side.
In a Slot-1 system design, pins A20M#, IGNNE#, INTR (LINT0) and NMI (LINT1) are shared with the external CPU clock ratio
straps. The schematic for this pin sharing is shown in Figure 2-36. These pins strap the setting of the CPU clock ratio during reset
and two clocks beyond the end of the RESET# pulse. Afterwards, the functionality of these signals will work as their names are
defined. (Note: This ratio select logic is also required in the Q-Spec Socket-370 system design.)
VT82C686A
(South Bridge)
A20M#
IGNNE#
INTR
NMI
CRESET#
From
VT82C694X

Figure 2-36. Schematic Example for Slot-1 CPU Internal/External Clock Ratio Pin Sharing

Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A

Table 2-9. Host Control Signals to South Bridge

South Bridge -- CPU
Signal Name I/O
A20M# OD A20 Mask
CPURST OD CPU Reset
FERR# I Numerical Coprocessor Error
IGNNE# OD Ignore Numerical Error
INIT OD Initialization
INTR OD CPU Interrupt
NMI OD Non-Maskable Interrupt
SLP# OD Sleep
STPCLK# OD Stop Clock
SMI# OD System Management Interrupt
VCC3
4.7K
JUMPER
ohm
1
3
5
7
U1
2
A1
4
A2
6
A3
8
A4
11
A5
13
A6
15
A7
17
A8
VCC3
1
OE0#
19
10K
OE1#
ohm
LVT244
U3
NC7S04
Description
2
4
6
8
18
Y1
16
Y2
14
Y3
12
Y4
9
Y5
7
Y6
5
Y7
3
Y8
VCC3
20
Note: LVT244, LVT07 and NC7S04 operate at the 3.3 volt interface.
44
VCC2_5
330
ohm
U2
A20M#
IGNNE#
INTR(LINT0)
NMI(LINT1)
LVT07
Motherboard Design Guidelines
Slot-1
CPU