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1.2 Apollo Pro133A Chipset Overview
The Apollo Pro133A chip set consists of the VT82C694X system controller (510-pin BGA) and the VT82C686A PCI to ISA
bridge (352-pin BGA). The features for both chips are listed below and a typical system block diagram is shown in this section.
1.2.1 VT82C694X Apollo Pro133A North Bridge Features
Apollo Pro133A (VT82C694X) is a Slot-1 and Socket-370 system logic north bridge with the addition of 133 MHz capability for
both the CPU and SDRAM interfaces. Apollo Pro133A may be used to implement both desktop and notebook personal computer
systems from 66MHz to 133MHz based on 64-bit Slot-1 (Intel Pentium-II) and Socket-370 (Intel and Celeron) processors. The
primary features of the Apollo Pro133A-North Bridge are:
•
Slot-1 or Socket-370 CPU (Front Side Bus) Interface (66 / 100 / 133MHz)
•
DRAM Memory Interface (66 / 100 / 133MHz)
•
AGP Bus Interface (66MHz)
•
PCI Bus Interface (33MHz)
•
Mobile Power Management
•
510-pin BGA Package
The DRAM interface supports eight banks of DRAMs (4 DIMM sockets) although VIA recommends implementation of three
DIMMs maximum for operation of the memory interface at 133 MHz. Total memory supported is 1.5 GB independent of the
number of DIMMs implemented. The DRAM controller supports standard Fast Page Mode (FPM) DRAM, EDO-DRAM,
Synchronous DRAM (SDRAM) and Virtual Channel SDRAM (VC SDRAM), in a flexible mix / match manner. The Synchronous
DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 66/100/133 MHz. The eight banks of
DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs. The DRAM controller also
supports optional ECC (single-bit error correction and multi-bit detection) or EC (error checking) capability separately selectable
on a bank-by-bank basis. The DRAM controller can run synchronous with the host CPU bus (66 /100 /133 MHz) or synchronous /
pseudo-synchronous with the AGP bus (66 / 133 MHz) with built-in PLL timing control. The DRAM interface can also run either
slower or faster than the CPU interface (both combinations of 66 / 100 MHz or both combinations of 100 / 133 MHz).
The AGP controller supports full AGP v2.0 capability for maximum bus utilization including 2x and 4X mode transfers, SBA
(SideBand Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four level post-write
request queue with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for deep pipelined
and split AGP transactions. A single-level GART TLB with 16 full associative entries and flexible CPU / AGP / PCI remapping
control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and Windows-98 /
NT5 miniport drivers are supported for interoperability with major AGP-based 3D and DVD-capable multimedia accelerators.
The VT82C694X supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) that are synchronous / pseudo-synchronous to
the CPU bus. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five
levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation,
forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are
supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged with PCI post
write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are
also implemented for further improvement of overall system performance.
For sophisticated power management, the Apollo Pro133A provides independent clock stop control for the CPU / SDRAM, PCI,
and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for
the SDRAM control signals for Suspend-to-DRAM operation. Coupled with the VT82C686A south bridge chip, a complete
power conscious PC main board can be implemented with no external TTLs.
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
2
Introduction
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