Apollo Pro133A Chipset Capacitive Decoupling; Dram Module Capacitive Decoupling; Figure 2-12. Decoupling Capacitor Placements For Vt82C694X And Vt82C686A; Figure 2-13. Decoupling Capacitor Placements For Dram Modules - VIA Technologies Apollo Pro133A Design Manual

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Design Guide - VT82C694X Apollo Pro133 with VT82C686A
We Connect We Connect

2.2.5.3 Apollo Pro133A Chipset Capacitive Decoupling

Decoupling capacitors for the VT82C694X and VT82C686A are shown in Figure 2-12. It is recommended to place decoupling
capacitors as close to the chips as possible and evenly distribute these capacitors around them. In most cases, the value of these
decoupling capacitors is 1uF, but 0.1uF capacitors are also acceptable. Similarly, this kind of placement can apply on other ASIC
chips, slots or sockets.

Figure 2-12. Decoupling Capacitor Placements for VT82C694X and VT82C686A

2.2.5.4 DRAM Module Capacitive Decoupling

The capacitive decoupling for SDRAM modules should be taken good care of since SDRAM modules running at 133MHz clock
consume much more power (about 1.76A for each double side DIMM module at maximum). Figure 2-13 shows a placement
example for SDRAM module decoupling.

Figure 2-13. Decoupling Capacitor Placements for DRAM Modules

Note: North Bridge controller (VT82C694X) is located at the north side of these DIMM Slots.
Preliminary Revision 0.5, November 19, 1999 20 Motherboard Design Guidelines