Figure 2-37. Layout Example Of Control Signal From South Bridge To Slot-1 Cpu; Figure 2-38. Layout Example Of Control Signal From South Bridge To Socket-370 Cpu - VIA Technologies Apollo Pro133A Design Manual

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A layout example for the remaining control signals between the VT82C686A chip and the Slot-1 CPU is shown in Figure 2-37.

Figure 2-37. Layout Example of Control Signal from South Bridge to Slot-1 CPU

No sharing circuitry is required in an S-Spec Socket-370 system design because the S-Spec Socket-370 CPU runs at marked ratio
only. A layout example for all control signals between the VT82C686A chip and the Socket-370 CPU is shown in Figure 2-38.
Currently, the voltage level of VCC_CMOS is 2.5V.
VT82C686A
(South Bridge)
STOPCLK#

Figure 2-38. Layout Example of Control Signal from South Bridge to Socket-370 CPU

The layout guidelines for these signals from the Slot-1 or Socket-370 CPU to the south bridge (VT82C686A) are listed below.
•
Each south bridge Open Drain (OD) output control signal to the CPU needs a 150 ~ 450 ohm pull-up which should be
placed as close to the VT82C686A chip as possible.
•
A minimum of 5 mils in width and a minimum of 10 mils in spacing are sufficient for good signal quality.
•
No specific limitation of the trace length for these control signals is required.
Preliminary Revision 0.5, November 19, 1999
VCC2_5
VT82C686A
(South Bridge)
INIT
SLP#
SMI#
STOPCLK#
FERR#
CPURST No Connect
VCC_CMOS
A20M#
IGNNE#
INTR
NMI
INIT
SLP#
SMI#
FERR#
CPURST No Connect
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
330
ohm
Layout these traces
as short as possible
330
ohm
Layout these traces as short as possible
45
Slot-1
CPU
INIT
SLP#
SMI#
STOPCLK#
FERR#
Socket-370
CPU
A20M#
IGNNE#
INTR(LINT0)
NMI(LINT1)
INIT
SLP#
SMI#
STOPCLK#
FERR#
Motherboard Design Guidelines