1. Manuals
  2. Brands
  3. VIA Technologies Manuals
  4. Network Hardware
  5. Apollo Pro133A
  6. Design manual

VIA Technologies Apollo Pro133A Design Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Design Guide
VT82C694X
Apollo Pro133A
with VT82C686A
South Bridge
Preliminary Revision 0.5
November 19, 1999
VIA TECHNOLOGIES, INC.

Advertisement

Table of Contents
loading

Related Manuals for VIA Technologies Apollo Pro133A

Summary of Contents for VIA Technologies Apollo Pro133A

  • Page 1 Design Guide VT82C694X Apollo Pro133A with VT82C686A South Bridge Preliminary Revision 0.5 November 19, 1999 VIA TECHNOLOGIES, INC.
  • Page 2 VT82C685, VT82C686B, VT82687, VT82C691, VT82C693, VT82C693A, VT82C694, VT82C694X, VT8501, VT8601, Super South, Apollo VP, Apollo VPX, Apollo VP2, Apollo VP3, Apollo MVP3, Apollo MVP4, Apollo P6, Apollo Pro, Apollo Pro133, Apollo Pro 133A, and Apollo ProMedia may only be used to identify products of VIA Technologies. PS/2 is a registered trademark of International Business Machines Corp.

  • Page 3: Revision History

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect EVISION ISTORY Document Date Revision Initials Release 11/19/99 Initial Release (Modified from DG694X&596BR070 and DG693A&686AR060) VL, JY, VH, RC, Preliminary Revision 0.5, November 19, 1999 Revision History...

  • Page 4: Table Of Contents

    Introduction ..............................1 1.1 About This Design Guide ..........................1 1.2 Apollo Pro133A Chipset Overview .........................2 1.2.1 VT82C694X Apollo Pro133A North Bridge Features ....................2 1.2.2 Super South (VT82C686A) Chipset Features....................... 3 1.2.3 System Block Diagram..............................4 1.3 System Design Recommendations ........................5 Motherboard Design Guidelines ........................

  • Page 5: Table Of Contents

    2.3.2.8 Miscellaneous Clock Signals ..........................37 2.3.2.9 Clock Trace Length Calculation.......................... 38 2.3.3 Routing Styles and Topology............................. 40 2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines ..............41 2.4.1 Host CPU Interface Layout and Routing Guidelines ....................41 2.4.1.1 Slot-1 Host Interface to North Bridge........................41 2.4.1.2 Socket-370 Host Interface to North Bridge......................
  • Page 6 B.1 Introduction ................................99 B.2 Layout Recommendations ............................100 B.2.1 Component Placement ............................100 B.2.2 Ground and Power Planes: ..........................103 B.2.3 Routing Guidelines............................. 105 Appendix C - Apollo Pro133A Reference Design Schematics................109 Preliminary Revision 0.5, November 19, 1999 Table of Contents...

  • Page 7: List Of Figures

    Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge ............4 Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View) ............7 Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View)..........8 Figure 2-3.
  • Page 8 Figure B-4. Power Layer Layout Example ..........................104 Figure B-5. Component Layer Layout Example ........................106 Figure B-6. Solder Layer Layout Example ..........................106 Figure C-1. Apollo Pro133A Reference Component Placement ....................110 Preliminary Revision 0.5, November 19, 1999 List of Figures...
  • Page 9 Table 2-5. Power-Up Configuration for VT82C686A ......................... 28 Table 2-6. Recommended Trace Width and Spacing........................29 Table 2-7. Apollo Pro133A Clock Synthesizer Requirements ...................... 30 Table 2-8. Apollo Pro133A System Clock Combinations ......................33 Table 2-9. Host Control Signals to South Bridge........................44 Table 2-10.
  • Page 10 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Preliminary Revision 0.5, November 19, 1999 List of Tables...

  • Page 11: Introduction

    1.1 About This Design Guide A brief description of each chapter is given below: Chapter 1: Introduction. An overview of Apollo Pro133A reference design features is given in this chapter along with general recommendations on Pro133A system design. Chapter 2: Motherboard Design Guidelines.

  • Page 12: Apollo Pro133A Chipset Overview

    1.2.1 VT82C694X Apollo Pro133A North Bridge Features Apollo Pro133A (VT82C694X) is a Slot-1 and Socket-370 system logic north bridge with the addition of 133 MHz capability for both the CPU and SDRAM interfaces. Apollo Pro133A may be used to implement both desktop and notebook personal computer systems from 66MHz to 133MHz based on 64-bit Slot-1 (Intel Pentium-II) and Socket-370 (Intel and Celeron) processors.

  • Page 13: Super South (Vt82C686A) Chipset Features

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 1.2.2 Super South (VT82C686A) Chipset Features The VT82C686A Super-IO PCI Integrated Peripheral Controller (PSIPC) is a high integration, high performance, power efficient and high compatibility device that supports Intel and non-Intel based processors plus PCI bus bridge functionality to make a complete Microsoft PC98-compliant PCI/ISA system.

  • Page 14: System Block Diagram

    We Connect 1.2.3 System Block Diagram A block diagram of a typical Apollo Pro133A based system with a VT82C686A South Bridge is shown in Figure 1-1. The Apollo Pro133A supports a single processor including 64-bit Slot-1 (Intel Pentium II ) or Socket-370 (Intel Celeron ) CPUs at 66 MHz, 100 MHz or the maximum 133MHz system bus frequency.

  • Page 15: System Design Recommendations

    We Connect 1.3 System Design Recommendations The VT82C694X Apollo Pro133A north bridge and VT82C686A south bridge form one of VIA's most optimized chipset combinations for single Slot-1or Socket-370 based PC systems. On an ATX form factor, for example, the optimized system specification for such a combination is listed below: •...
  • Page 16 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Preliminary Revision 0.5, November 19, 1999 Introduction...

  • Page 17: Motherboard Design Guidelines

    2.1.1 Apollo Pro133A North Bridge Ballout Assignment Ballout of the Apollo Pro133A North Bridge is designed to minimize the number of crossover signals. Figure 2-1 shows the four major signal group quadrants of the Apollo Pro133A Ballout. They are Host, Memory, AGP and PCI interfaces. Please refer to the VT82C694X datasheet for more details on ball assignments.

  • Page 18: Super South" South Bridge Ballout Assignment

    Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View) Package Information: • The VIA VT82C694X Apollo Pro133A North Bridge is a 510-pin Ball Grid Array (BGA) package. The package size is 35mm x 35mm and the grid matrix is 26x26. •...

  • Page 19: Motherboard Description

    2.2.1 Slot-1 Motherboard Placement and Routing For Slot-1 CPU and Apollo Pro133A PC motherboard designs, two proposed placements and group signal routings for the two most popular form factors (ATX and micro-ATX) are shown in figures 2-3 and 2-4 respectively. Detailed layout guidelines and signal routings for the Pro133 chipset will be addressed later in section 2.4.

  • Page 20: Atx Form Factor For Slot-1 System

    2.2.1.1 ATX Form Factor for Slot-1 System A proposed component placement and signal group routing for an Apollo Pro133A ATX form factor system design is illustrated in Figure 2-3. The major components on the board are single Slot-1 CPU, five PCI slots, one AMR, one ISA slot and three DIMM slots.

  • Page 21: Micro Atx Form Factor For Slot-1 System

    2.2.1.2 Micro ATX Form Factor for Slot-1 System A proposed component placement and signal group routings for an Apollo Pro133A micro-ATX system design is illustrated in Figure 2-4. The major components on the board are single Slot-1 CPU, two PCI slots, one AMR, one ISA slot and two DIMM slots.

  • Page 22: Socket-370 Motherboard Placement And Routing

    2.2.2 Socket-370 Motherboard Placement and Routing For Socket-370 CPU and Apollo Pro133A PC motherboard designs, two proposed placements and group signal routings for the two most popular form factors (ATX and micro-ATX) are shown in figures 2-5 and 2-6 respectively. Detailed layout guidelines and signal routings for the Pro133A chipset will be addressed later in section 2.4.

  • Page 23: Atx Form Factor For Socket-370 System

    2.2.2.1 ATX Form Factor for Socket-370 System A proposed component placement and signal group routing for an Apollo Pro133A ATX form factor system design is illustrated in Figure 2-5. The major components on the board are single Socket-370 CPU, five PCI slots, one AMR, one ISA slot and three DIMM slots.

  • Page 24: Micro Atx Form Factor For Socket-370 System

    2.2.2.2 Micro ATX Form Factor for Socket-370 System A proposed component placement and signal group routing for an Apollo Pro133A micro-ATX system design is illustrated in Figure 2-6. The major components on the board are single Socket-370 CPU, two PCI slots, one AMR, one ISA slot and two DIMM slots.

  • Page 25: Printed Circuit Board Description

    2.2.3 Printed Circuit Board Description A brief description of the Printed Circuit Board (PCB) for an Apollo Pro133A based system is provided in this section. From a cost-effectiveness point of view, a four-layer board is recommended for the motherboard design. For better quality, a six-layer board is preferred.

  • Page 26: Six-Layer Board

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.2.3.2 Six-Layer Board Figure 2-8 illustrates an example of a six-layer stack-up with 4 signal layers and 2 power planes. The layer sequence of component-ground-internal1-internal2-power-solder is the most common stack-up arrangement from top to bottom. It is recommended to place a 5~6 mil substrate between the signal layer and the power plane and place 30~35 mil substrate between two internal layers.

  • Page 27: On Board Power Regulation

    2.2.5 Capacitive Decoupling This section describes issues related to the capacitive decoupling of a Slot-1 CPU, Socket-370 CPU, Apollo Pro133A chipsets and DRAM Modules. It is well known that appropriate decoupling capacitors are required to provide a stable power source to the CPU, the ASIC and all other components on a motherboard.

  • Page 28: Single Slot-1 Processor Capacitive Decoupling

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.2.5.1 Single Slot-1 Processor Capacitive Decoupling Figure 2-10 shows a suggested decoupling capacitor placement for the Slot-1 CPU. The isolation region between any two of the VCC_CORE (Core voltage 2.1V~3.3V) island, the VCC3 (I/O voltage 3.3V) island, the VTT (GTL+ termination voltage 1.5V) island and the VCC5 (5V) should be at least 30 mil wide.

  • Page 29: Single Socket-370 Processor Capacitive Decoupling

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.2.5.2 Single Socket-370 Processor Capacitive Decoupling A suggested decoupling capacitor placement for the Socket-370 CPU is shown in Figure 2-11. The high frequency decoupling capacitors (0.1uF and 1uF) should be located as close to the power and ground pins of the Socket-370 as possible. One hundred and twelve 56 ohm termination resistors are required for the GTL+ bus (HD[63:0], HA[31:3] and 19 host control signals) on the motherboard.

  • Page 30: Apollo Pro133A Chipset Capacitive Decoupling

    We Connect We Connect 2.2.5.3 Apollo Pro133A Chipset Capacitive Decoupling Decoupling capacitors for the VT82C694X and VT82C686A are shown in Figure 2-12. It is recommended to place decoupling capacitors as close to the chips as possible and evenly distribute these capacitors around them. In most cases, the value of these decoupling capacitors is 1uF, but 0.1uF capacitors are also acceptable.

  • Page 31: Power Plane Partitions

    2.2.6 Power Plane Partitions The required voltage sources in an Apollo Pro133A system design are: +/-12V, +/-5V, CPU core voltage (1.3V~3.3V defined by the five voltage identification pins of the Slot-1 or Socket-370 CPU), 3.3V, 2.5V and 1.5V. The power layer is partitioned into several power islands with five major power sources: VCC_CORE (CPU core voltage), VCC3 (3.3V), VTT (1.5V GTL+...

  • Page 32: Figure 2-15. Micro-Atx Power Plane Partitions For Slot-1 System

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Back Panel Area VCC5 Island VCC5 Island VCC_CORE Island VCC3 Island VTT Island 694X VDDQ Island 510-PIN GEN. VCC3 Island VT82C 686A IDE1 IDE2 VCC5 Island VCC5 Island Figure 2-15.

  • Page 33: Power Plane Partitions For Socket-370 Motherboard

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.2.6.2 Power Plane Partitions for Socket-370 Motherboard Figure 2-16 shows the power plane partitions on a typical ATX form factor. The island associated with VCC_CORE covers the whole area of the PPGA socket for the Socket-370 CPU.

  • Page 34: Figure 2-17. Micro-Atx Power Plane Partitions For Socket-370 System

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Back Panel Area VCC5 Island VCC5 Island VCC_CORE Island VCC3 Island 694X GEN. VDDQ Island 510-PIN VCC3 Island VT82C 686A IDE1 IDE2 VCC5 Island VCC5 Island Figure 2-17.

  • Page 35: Chipset Power And Ground Layout Recommendations

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.2.7 Chipset Power and Ground Layout Recommendations This section shows the recommended layout of the power plane and the ground plane on each layer for the two VIA BGA chips (VT82C694X and VT82C686A).

  • Page 36: Figure 2-19. Vt82C686A Power And Ground Layout

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect (a) Component Layer (b) Ground Layer (c) Power Layer (d) Solder Layer Figure 2-19. VT82C686A Power and Ground Layout Notes: 1. In Figure 2-19 (b) and (c), a black round dot represents a via with no connection to the specified layer and a white round dot represents a via with a connection to the specified layer.

  • Page 37: Power Up Configuration

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.2.8 Power Up Configuration During system restart and power up, system configuration information is latched at the rising edge of the RESET# signal. All signals used to select power-up strap options are connected to either internal pull-up or pull-down resistors of minimum 50K ohms (maximum is 150K ohm).

  • Page 38: Vt82C694X Power Up Strappings

    2.2.8.1 VT82C694X Power Up Strappings Internal configuration registers of Apollo Pro133A digital core logic are based on the status of memory address lines (MAB[12:11]#, MAB10, MAB[9:6]#) and Host address lines (A15# and A7#). These memory address signals are pulled up or pulled down with internal resistors on their I/O buffers to determine the default configurations.

  • Page 39: General Layout And Routing Guidelines

    2.3.1 Trace Attribute Recommendations For most signal traces on an Apollo Pro133A motherboard layout, 5-mil trace width and 10-mil spacing are advised. To reduce trace inductance, minimum power trace width is set at 30 mils. As a quick reference, recommended trace width and spacing for different trace types are listed in Table 2-6.

  • Page 40: Apollo Pro133A Clock Layout Recommendations

    We Connect 2.3.2 Apollo Pro133A Clock Layout Recommendations 2.3.2.1 Clock Requirements The requirements of the system clock synthesizer for an Apollo Pro133A based system design are listed in Table 2-7. Table 2-7. Apollo Pro133A Clock Synthesizer Requirements Clock Signal Type...

  • Page 41: Clocking Scheme

    The 17 (66 / 100 / 133MHz) SDRAM clocks are generated from a clock buffer inside the system clock synthesizer. They are controlled by the SDRAM clock output (DCLKO) provided by the Apollo Pro133A North Bridge. The VT82C694X (North Bridge) has a built-in de-skew Phase Lock Loop (PLL) circuitry for optimal skew control within and between clocking regions.

  • Page 42: Clock Routing Considerations

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.3.2.3 Clock Routing Considerations Clock routing guidelines are listed below: • The recommended range of a clock trace width is between 15 mils and 20 mils. •...

  • Page 43: System Clock Combinations

    2.3.2.4 System Clock Combinations The major clock combinations for an Apollo Pro133A based system are listed in Table 8. Clock frequencies for the AGP clock and PCI clock are 66MHz and 33MHz respectively. Various clock combinations for the CPU clock and the SDRAM clock are determined by power-up strap options on MAB12# and MAB8#.

  • Page 44: Host Cpu Clock And Sdram Clock Signals

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.3.2.5 Host CPU Clock and SDRAM Clock Signals Layout recommendations for host clocks and SDRAM clocks for Slot-1 and Socket-370 CPUs are shown in Figure 2-26 and 2-27 respectively.

  • Page 45: Figure 2-27. Host Clock And Sdram Clock Layout Recommendations For Socket-370 Systems

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 0 ~ 33 Socket-370 10 ~ 33 pF CPUCLK VT82C694X HCLK HCLK 0 ~ 33 DOUT DCLKO SDCLKIN (as short as possible) 10 ~ 33 pF (near the chip) + 4.5"...

  • Page 46: Agp Clock Signals

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.3.2.6 AGP Clock Signals Layout recommendations for the AGP clock are shown in Figure 2-28. Typically, 22 ohm series terminations are recommended for the AGP clock. A typical 22 pF bypass capacitor is also required for the AGP clock (GCLKO) to the AGP slot. Depending on how the system is designed, the value of the bypass capacitors for the PCI clocks may vary.

  • Page 47: Pci Clock Signals

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.3.2.7 PCI Clock Signals Layout recommendations for the PCI clocks are shown in Figure 2-29. Typically, 22 ohm series terminations are recommended for all PCI clocks. A typical 22 pF bypass capacitor is also required for each PCI clock. Depending on how the system is designed, the value of the bypass capacitors for the PCI clocks may vary.

  • Page 48: Clock Trace Length Calculation

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.3.2.9 Clock Trace Length Calculation The calculation is based on the recommended placements shown in sections 2.2.1 and 2.2.2. A different component placement may result in a different calculation for the clock trace length. CPU Clock Trace Length Calculation for Slot-1 System Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Slot-1 CPU (CPUCLK) and North Bridge (HCLK) as short as possible.
  • Page 49 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect AGP Clock Trace Length Calculation Pre-route AGP clock traces from the pin GCLKO of the VT82C694X to the AGP slot as short as possible. Then the trace length for the signal GCLK should be the GCLKO trace length plus 3 inches.

  • Page 50: Routing Styles And Topology

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.3.3 Routing Styles and Topology High-speed bus signals are sensitive to transmission line stubs, which can result in ringing on the rising edge caused by the high impedance of the output buffer in the high state.

  • Page 51: Vt82C694X Apollo Pro133A Layout And Routing Guidelines

    Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines 2.4.1 Host CPU Interface Layout and Routing Guidelines The GTL+ signals (host address bus, host data bus and host control signals) are typical point-to-point connections between CPU and North Bridge in a Slot-1 or Socket-370 system design.

  • Page 52: Socket-370 Host Interface To North Bridge

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.4.1.2 Socket-370 Host Interface to North Bridge The recommended topology for the Socket-370 host signals to North Bridge (VT82C694X) is shown in Figure 2-34. For signal quality considerations, the trace length of the host signals should be minimized.

  • Page 53: Figure 2-35. Host Interface Layout Example Between Socket-370 And Vt82C694X

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect (a) Component Side (b) Solder Side Figure 2-35. Host Interface Layout Example between Socket-370 and VT82C694X Preliminary Revision 0.5, November 19, 1999 Motherboard Design Guidelines...

  • Page 54: Cpu Host Interface To South Bridge

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.4.1.3 CPU Host Interface to South Bridge The host control signals from the Slot-1 or Socket-370 CPU to the south bridge (VT82C686A) are listed in Table 2-9. Except for FERR#, all signals are open drain (OD).

  • Page 55: Figure 2-37. Layout Example Of Control Signal From South Bridge To Slot-1 Cpu

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect A layout example for the remaining control signals between the VT82C686A chip and the Slot-1 CPU is shown in Figure 2-37. VCC2_5 Slot-1 VT82C686A (South Bridge) INIT INIT SLP#...

  • Page 56: Memory Subsystem Layout And Routing Guidelines

    The maximum DRAM installation is four DIMM slots. Three layout examples (Daisy Chain Ordering) for all DRAM buses and control signals between the Apollo Pro133A North Bridge and four, three or two DRAM DIMM slots are shown in Figure 2-39, 2- 40 and 2-42 respectively.

  • Page 57: Figure 2-39. Daisy Chain Routing For Four-Dram Dimm Slots

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect VT82C694X DIMM4 DIMM3 DIMM2 DIMM1 (North Bridge) 0.4" < L3 < 0.5" 0.4" < L4 < 0.5" 2" < L1 < 2.5" 0.4" < L2 < 0.5" MD[63:0] MECC[7:0] CASA[7,6,4:2,0]#...

  • Page 58: Figure 2-40. Daisy Chain Routing For Three-Dram Dimm Slots

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect VT82C694X DIMM3 DIMM2 DIMM1 (North Bridge) 0.4" < L3 < 0.5" 2" < L1 < 3" 0.4" < L2 < 0.5" MD[63:0] MECC[7:0] CASA[7,6,4:2,0]# 2" < L4 < 3.5" MAA[14:0] SWEA# SRASA#...

  • Page 59: Figure 2-41. T-Style Routing For Three-Dram Dimm Slots

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect DIMM3 DIMM2 DIMM1 VT82C694X (North Bridge) 0.4" < L3 < 0.5" 0.4" < L2 < 0.5" 2" < L1 < 3.5" MD[63:0] MECC[7:0] CASA[7,6,4:2,0]# 2" < L4 < 3.5" 0.4"...

  • Page 60: Dram Reference Layout

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect VT82C694X DIMM2 DIMM1 (North Bridge) 2" < L1 < 3.5" 0.4" < L2 < 0.5" MD[63:0] MECC[7:0] CASA[7:0]# MAA[14:0] SWEA# SRASA# SCASA# 2" < L3 < 4" RASA[1:0]# RASB[1:0]# RASA[3:2]#...

  • Page 61: Figure 2-44. Layout Example Of Three-Dram Dimm Slots

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect The reference layout for three-DRAM DIMM slots is shown in Figure 2-44 below. In this layout example, no DRAM trace is over 4 inches long and those traces are also evenly distributed. (a) Component Side (b) Solder Side Figure 2-44.

  • Page 62: Agp (4X Mode) Interface Layout And Routing Guidelines

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.4.3 AGP (4X Mode) Interface Layout and Routing Guidelines This section describes layout and routing guidelines to insure a robust AGP 4X mode interface design. The following guidelines will help insure that the AGP specification can be met.

  • Page 63: Vref Characteristics For Agp 4X Mode

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.4.3.2 Vref Characteristics for AGP 4X Mode Vref is a DC voltage reference signal used to set the input sense level on the AGP bus. Vref is set at 0.5 x VDDQ (between 0.48 x VDDQ and 0.52 x VDDQ) for AGP 4X mode.

  • Page 64: Figure 2-47. Vddq Voltage-Switching Application Circuit

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Figure 2-47 shows an application example for the VDDQ Voltage-Switching circuit shown in Figure 2-46. Signal TYPEDET# is used to determine the VDDQ voltage level (1.5V or 3.3V) for the AGP interface. When TYPEDET# is high, Q1 is always turned on.

  • Page 65: Agp Vddq Power Plane Partition

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.4.3.4 AGP VDDQ Power Plane Partition By referring to the power plane partition examples in figures 2-15 to 2-16, the power plane for the AGP slot should be separated from the remaining power planes on the motherboard.

  • Page 66: Optimized Layout And Routing Recommendations

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.4.3.5 Optimized Layout and Routing Recommendations It is strongly recommended to maintain the trace length of all AGP (especially Data and Strobe) signals less than 4 inches. It is always best to reduce line mismatch to add to the timing margin.

  • Page 67: Figure 2-50. Agp 4X Interface Layout Example

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect (b) Solder Side Figure 2-50. AGP 4X Interface Layout Example Notes: 1. Most Decoupling capacitors are placed on the left-hand side of the AGP slot in Figure 2-50 (a). 2.

  • Page 68: Pci Interface Layout And Routing Guidelines

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.4.4 PCI Interface Layout and Routing Guidelines It is recommended that the VT82C694X and VT82C686A be placed at both ends of the PCI bus for better signal termination. A topology example of the AGP and PCI buses on an ATX form factor is shown in Figure 2-51 below.

  • Page 69: Super South (Vt82C686A) Layout And Routing Guidelines

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.5 Super South (VT82C686A) Layout and Routing Guidelines 2.5.1 USB controller The Universal Serial Bus (USB) provides a bi-directional, isochronous, hot-attachable Plug and Play serial interface for adding external peripheral devices such as game controllers, communication devices, and input devices on a single bus.

  • Page 70: Figure 2-53. Usb Differential Signal Routing Example

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect The layout guidelines for USB are listed below. • Each pair of USB data signals is required to be parallel to each other with the same trace length. •...

  • Page 71: Ac'97 Link And Game/Midi Ports

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.5.2 AC’97 Link and Game/MIDI Ports Table 2-13 shows a brief description of the signals of AC'97 Link Controller and Game Ports. All those signals are multi-function pins with the second IDE channel bus.

  • Page 72: Game/Midi Ports

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect VT1611A VT82C686A (Audio Codec) (South Bridge) 22 ohm BITCLK BITCLK SDIN SDATA_IN SDIN2 10K ohm 22 ohm ACRST# RESET# SYNC SYNC SDOUT SDATA_OUT AC'97 CONTROLLER AC'97 Codec Figure 2-54.

  • Page 73: Hardware Monitoring

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.5.3 Hardware Monitoring The hardware monitoring interface includes five positive voltage sensing inputs (four external and one internal), three temperature sensing inputs (two external and one internal), two fan-speed monitoring inputs and one chassis intrusion detection input. Programmable control, status, monitor and alarm are supported by the VT82C686A for flexible desktop management.

  • Page 74: Integrated Super Io Controller

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Voltage Monitoring Typically VCC2 (core voltage of the CPU), VCCI (2.5V, core voltage of the VT82C694X), VCC3 (3.3V), 5V, and +12V are the five monitored voltage inputs. VCC2 and VCCI can be directly connected to the inputs. The +5V and 12V inputs should be attenuated with external resistors to any desired value within the input range.

  • Page 75: System Management Bus Interface

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.5.5 System Management Bus Interface The I2C bus signal pair of the VT82C686A will handle all I2C buses to other on-board devices such as the Clock Synthesizer and the three DIMM slots.

  • Page 76: Ide

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.5.6 IDE Both Primary and secondary IDE channels have their own control signals. The Primary IDE channel has a dedicated data bus. However, the secondary IDE data bus is multiplexed with an Audio/Game port or it can share ISA address bus SA[15:0] as SDD[15:0].

  • Page 77: Figure 2-59. Ide Interfaces Layout Guidelines

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Dual channel master mode PCI supports four Enhanced IDE devices. The transfer rate for each device can support up 33 MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface. Transmission line effects and signal crosstalk emerge in the IDE related signals.

  • Page 78: Figure 2-60. Ultra Dma/66 Placement And Routing Example

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Ultra DMA/66 Interface Layout Guidelines VT82C686A supports Ultra DMA/66 IDE interfaces on both Primary IDE channel (IDE1) and Secondary IDE channel (IDE2). A Micro-ATX component placement example for implementing the Ultra DMA/66 interface (option 2) is shown in Figure 2-60. The detailed placement for the VT82C686A chip and two IDE connectors is illustrated in the lower left corner of the figure.

  • Page 79: Figure 2-61. Ultra Dma/66 Application Circuit

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect The application circuit of the ultra DMA/66 IDE interface is shown in Figure 2-61. The 80-conductor cable, required by the ultra DMA/66 IDE interface, is the major difference from the 40-conductor cable of the current IDE interface. For the detection of the 80-conductor cable, pin 34 (CBLID) of IDE connector may be used to provide a signal state from an ultra DMA/66 device to a GPI pin of the South Bridge Controller.

  • Page 80: Suspend To Drm

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.5.7 Suspend to DRM Power-on-suspend (POS), Suspend-to-RAM (STR) and Suspend-to-Disk (STD) or so called Soft-off are three different suspend states supported by the VT82C686A. These suspend functions are implemented not only in a notebook PC design but also in a desktop PC design.

  • Page 81: Str Power Plane Control

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 2.5.7.2 STR Power Plane Control VT82C686A controls the system entering the various suspend states through the suspend control signals listed in Table 2-14. Three power plane control signals (SUSA#, SUSB# and SUSC#) are provided to turn off more system power planes as the system moves to deeper power-down states from normal operation to POS (only SUSA# asserted), to STR (both SUSA# and SUSB# asserted), and to STD (all three SUS# signals asserted).
  • Page 82 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Preliminary Revision 0.5, November 19, 1999 Motherboard Design Guidelines...

  • Page 83: Timing Analysis And Simulation

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect IMING NALYSIS AND IMULATION The 133 MHz timing analysis here will provide a basis for the concept of trace length limitation for some high speed buses and control signals such as the CPU address bus (A[31:3]).

  • Page 84: Figure 3-2. Cpu Post Write To Sdram (Sl=2)

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect CCLK cccccccccccccccccccccccccccccccccccc ADS# hhfrhfrhfrhhhhhhhhhhhhhhhhhhhhhhhhhh HREQ# zznxonxonxozzzzzzzzzzzzzzzzzzzzzzzzz zznxonxonxozzzzzzzzzzzzzzzzzzzzzzzzz zzzzzzzznozznozznozzzzzzzzzzzzzzzzzz DBSY# hhhhhhhfllrfllrfllrhhhhhhhhhhhhhhhhh DRDY# hhhhhhhflllllllllllrhhhhhhhhhhhhhhhh HTRDY# hhhhhflrflrflrhhhhhhhhhhhhhhhhhhhhhh zzzzzzznxxxxxxxxxxxozzzzzzzzzzzzzzzz hhhhhhhfrfrhhfrhhfrhhhhhhhhhhhhhhhhh SRAS# hhhhhhhfrhhhhhhhhhhhhhhhhhhhhhhhhhhh SCAS# hhhhhhhhhfrhhfrhhfrhhhhhhhhhhhhhhhhh SWE# hhhhhhhhhfrhhfrhhfrhhhhhhhhhhhhhhhhh DQM# hhhhhhhhhflllllllllllrhhhhhhhhhhhhhh zzzzzzzzznxxxxxxxxxxxozzzzzzzzzzzzzz Consideration: A: Be careful of the MD data length B: Be careful of the CPU data length C: Be careful of the CPU address length...

  • Page 85: Electrical Specifications

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect LECTRICAL PECIFICATIONS This section describes the electrical specifications of the VT82C694X. 4.1 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation is not implied under the ratings listed in Table 4-1.

  • Page 86: Dc Characteristics

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 4.3 DC Characteristics DC characteristics of the VT82C694X are shown in Table 4-3. Table 4-3. DC Characteristics Symbol Parameter Unit Condition Input Low Voltage -0.5 +0.8 Input High Voltage +2.0 +0.5...

  • Page 87: Signal Connectivity And Design Checklist

    The signal connectivity table provides board designers a quick reference of signal connections. And it can be used to review schematics of an Apollo Pro133A system. The design checklist can provide a quick way to review the PCB layout of an Apollo Pro133A system.

  • Page 88: Vt82C694X Apollo Pro133A North Bridge

    Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 5.2 VT82C694X Apollo Pro133A North Bridge The connectivity for each signal of the VT82C694X North Bridge is listed in Table 5-1. Motherboard designers can use this table as a quick reference to review their schematics.
  • Page 89 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect PCI BUS INTERFACE Signal Name Connection CBE[3:0]# Connect to VT82C686A and PCI slots. AD[31:0] Same as the above. FRAME# Connect between VT82C694X, PCI slots, and VT82C686A. 2.7K ohm pull-up to VCC5. IRDY# Same as the above.
  • Page 90 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect CLOCK AND RESET CONTROL Signal Name Connection HCLK Connect to the CPU clock output of the system clock synthesizer. DCLKO Connect to the SDRAM clock input of the system clock synthesizer. DCLKWR Connect to the SDRAM clock output of the system clock synthesizer.

  • Page 91: Super South" South Bridge Controller

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 5.3 "Super South" South Bridge Controller The connectivity for each signal of VT82C686A South Bridge is listed in Table 5-2. Motherboard designers can use this table as a quick reference to review their schematics.
  • Page 92 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect ISA BUS INTERFACE Signal Name Connection SA[19:16] Connect to ISA slots and BIOS ROM. 4.7K ohm pull-up to VCC. Connect SA[19:17] also to LA{19:17}. SA[15:0]/SDD[15:0] Connect to ISA slots and BIOS ROM. 4.7K ohm pull-up to VCC. And connected to secondary IDE connector through two 74F245 ICs.
  • Page 93 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect USB INTERFACE Signal Name Connection USBP0+, Connect to USB(0) connector. 47pF capacitor to ground with 27 ohm resistor, and then USBP0- 15K ohm resistor to ground. These passive components should be placed as close to VT82C686A as possible OC0#/ Connect to the corresponding USB(0) over-current detection voltage divider.
  • Page 94 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect ULTRA DMA-66 ENHANCED IDE INTERFACE Signal Name Connection PDIOR# Connected to primary IDE connector through a 33 ohm series resistor. PDIOW# Same as the above. PDDACK# Same as the above.
  • Page 95 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect PARALLEL PORT INTERFACE Signal Name Connection PD[7:0] Connect to the printer connector. 4.7K ohm pull-up to VCC and a 180pF decoupling capacitor to ground. These passive components should be placed near the connector. AUTOFD# Same as the above.
  • Page 96 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect SERIAL PORTS AND INFRARED INTERFACE Signal Name Connection TXD1 Connected to a corresponding 9-pin serial connector (usually COM1) through a serial RS232 interface buffer and a 330pF decoupling capacitor to ground. RXD1 Same as the above.
  • Page 97 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect GENERAL PURPOSE INPUTS Signal Name Connection GPI0/IOCHCK# 4.7K ohm pull-up to VCC3 if no multiplexed function is applied. GPI1/IRQ8# 10K ohm pull-up to 3VSB if its function is applied. Same, if not applied. GPI2/BATLOW# 4.7K ohm pull-up to VCC3 if no multiplexed function is applied.
  • Page 98 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect GENERAL PURPOSE I/O Signal Name Connection GPIOA(GPIO8) 4.7K ohm pull-up to VCC3 if no multiplexed function is applied. GPIOB(GPIO9)/FAN2 Same as the above. GPIOC(GPIO10)/ Same as the above. CHAS GPIOD(GPIO11) Same as the above.
  • Page 99 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect POWER MANAGEMENT Signal Name Connection PME#/THRM/GPI5 10K ohm pull-up to 3VSB if the function is not applied. PWRBTN# Connect to Power Button circuitry. SLPBTN#/IRQ6/GPI4 10K ohm pull-up to VCC3 if the function is not applied. RSMRST Connect to Resume Reset circuitry.

  • Page 100: Apollo Pro-133A Design Checklist

    5.4.1 General Layout Considerations Checklist For most signal traces on an Apollo Pro133A motherboard layout, 5-mil trace width and 10-mil spacing are advised. To reduce trace inductance, minimum power trace width is set at 30 mils. As a quick reference, recommended trace width and spacing for different trace types are listed in Table 5-3.

  • Page 101: Decoupling Recommendations Checklist

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 5.4.3 Decoupling Recommendations Checklist The high frequency and bulk decoupling capacitor distributions for major components are described in this section. Here, the high frequency decoupling capacitors include 0.1uF (0603), 1uF (0805) and 4.7uF (1206) SMD ceramic capacitors. The bulk decoupling capacitors include 10uF, 100uF and 1000uF electrolytic capacitors.

  • Page 102: Clock Trace Checklist

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 5.4.4 Clock Trace Checklist The general clock routing guidelines are listed below: • The recommended range of a clock trace width is between 15 mils and 20 mils. •...
  • Page 103 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect SDRAM Clock Trace Length Calculation Pre-route SDRAM clock traces (SDCLK0~SDCLK15) from the system clock synthesizer to the DIMM slots as short as possible. The length of all SDRAM clocks will be based on the longest one (L ).

  • Page 104: Signal Trace Attribute Checklist

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect 5.4.6 Signal Trace Attribute Checklist The maximum accumulated trace length as a brief layout reference for high-speed or critical signal groups (e.g. host and memory) is listed in Table 5-4. The accumulated trace length represents the total trace length or the length sum of two traces before and after a damping resistor.

  • Page 105: Appendices

    No license, express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. VIA Technologies, Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification.
  • Page 106 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Preliminary Revision 0.5, November 19, 1999 Appendices...

  • Page 107: Appendix A - Spkr Strapping Application Circuits

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Appendix A - SPKR Strapping Application Circuits Power-up strapping for the VT82C686A SPKR pin (pin V5) determines the function of the Secondary IDE disk data bus pins (SDD[15..0]) to be either SDD[15..0] (SPKR strapped low) or Audio/Game port functions (SPKR strapped high).
  • Page 108 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Preliminary Revision 0.5, November 19, 1999 Appendix A - SPKR Strapping Application Circuits...

  • Page 109: Appendix B - Audio Codec And Game/Midi Port Layout Guidelines

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines B.1 Introduction This document describes the Printed Circuit Board (PCB) layout recommendations for VIA VT1611A (AC’97 audio codec) and Game/MIDI port in a motherboard design.

  • Page 110: Layout Recommendations

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect B.2 Layout Recommendations In this section, the layout recommendations on component placement, ground and power plane partitions and routing guidelines are described in detail. The PCB layer sequence used here is Signal (Component)-Ground-Power-Signal (Solder). B.2.1 Component Placement AC’97 Audio Codec and Audio Amplifier AC’97 audio codec (VT1611A) and audio amplifier (TPA122) are two major components in the audio codec circuitry.

  • Page 111: Table B-1. Decoupling Capacitor List

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect These high frequency decoupling capacitors should be routed on the component layer with wide traces to reduce impedance and placed on their respective ground plane. Low frequency decoupling capacitors (basically greater than or equal to 10uF, Electrolytic or Tantalum) are used to prevent power supply droop during load transient.

  • Page 112: Table B-3. Ac-Coupling Capacitors For Audio Input Signals

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Table B-3. AC-Coupling Capacitors for Audio Input Signals Audio Output Signals AC-Coupling Capacitors Note LINE_OUT_L LINE_OUT_R MONO_OUT None LNLVL_OUT_L None LNLVL_OUT_R None Notes 1. Use all ac-coupling capacitors in 1206 package. 2.

  • Page 113: Ground And Power Planes

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect B.2.2 Ground and Power Planes: It is recommended to include partitioned digital and analog power planes directly over their respective ground planes. The power- ground sandwich with a substrate separation can provide an extremely effective, low ESR & ESL bypass capacitance. The audio IC leads will have pads and vias that go directly to the appropriate plane for power and ground.

  • Page 114: Figure B-4. Power Layer Layout Example

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Table B-4. Signal Groups Associated with Their Audio Ground Plane Ground Planes Audio Signals Note Audio input signals: AUX_L. AUX_R, VIDEO_L, VIDEO_L, VIDEO_R, CD_L. CD_R, CD_GND, LINE_IN_L, LINE_IN_OUT, MIC1, MIC2, PHONE_IN GND_AUD Audio reference signals: MONO_OUT, VREFOUT, VREF, AFILT1 and AFILT2 Analog Power signals: AVDD1, AVDD2, AVSS1 and AVSS2...

  • Page 115: Routing Guidelines

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect B.2.3 Routing Guidelines Routing to VDD, VREF, AFILT and FILT capacitors All high frequency decoupling, reference high frequency decoupling and filter capacitors must be routed on the same layer as the codec.

  • Page 116: Figure B-5. Component Layer Layout Example

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Figure B-5. Component Layer Layout Example Figure B-6. Solder Layer Layout Example Preliminary Revision 0.5, November 19, 1999 Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines...

  • Page 117: Table B-5. Routing Guidelines For Signal Nets

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Table B-5 and Table B-6 show the layout guideline summary for signal and power/ground nets respectively in the reference schematic. Table B-5. Routing Guidelines for Signal Nets Net Name Routing Guidelines Note...
  • Page 118 Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Preliminary Revision 0.5, November 19, 1999 Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines...

  • Page 119: Appendix C - Apollo Pro133A Reference Design Schematics

    Appendix C - Apollo Pro133A Reference Design Schematics Apollo Pro133A Reference design schematics are shown in the following 20 pages. The component placement for this reference design is shown in Figure C-1. The system specification for this motherboard design is listed below: •...

  • Page 120: Figure C-1. Apollo Pro133A Reference Component Placement

    Technologies, Inc. Design Guide - VT82C694X Apollo Pro133 with VT82C686A We Connect We Connect Figure C-1. Apollo Pro133A Reference Component Placement Preliminary Revision 0.5, November 19, 1999 Appendix C - Apollo Pro133A Reference Design Schematics...
  • Page 121 STR OPTION CIRCUITS | 16.SCH | 17.SCH | 18.SCH | 19.SCH | 20.SCH VIA TECHNOLOGIES ASSUMES NO RESPONSIBILITY FOR ANY ERRORS VIA TECHNOLOGIES, INC. IN DRAWING THESE SCHEMATICS. THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE. Title COVER SHEET COPYRIGHT 1999 VIA TECHNOLOGIES INCORPORATED.
  • Page 122 -SLP FLUSH TRST -CPUINIT VCC2_5 -CPUINIT INIT -CPURST 2.5V -CPURST RESET THERMTRIP 2.5V VCCP_GD PWRGOOD CPUCLK CPUCLK BCLK VIA TECHNOLOGIES, INC. VID0 VID0 Title VID1 VID1 VCC2_5 SLOT 1 VID2 BSEL1 VID2 VID3 BSEL1 VID3 Size Document Number VID4 VID4...
  • Page 123 -HTRDY HTRDY -RS0 -RS0 -RS1 -RS1 -RS2 -RS2 -CPURST -CPURST CPURST -BREQ0 -BREQ0 BREQ0 VT82C694X-A HCLK *near to chip VCC3 A[3..31] A[3..31] VIA TECHNOLOGIES, INC. Title NORTH BRIDGE VT82C694A/X-A Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999 Sheet...
  • Page 124 AC23 CKE4 CKE4 CKE4/CSB6 AF24 AD25 CKE5 DCLKWR DCLKWR CKE5 CKE5/CSB7 DCLKWR C156 *VSSQQ VT82C694X-B GCLKIN VIA TECHNOLOGIES, INC. GCLK DCLKO Title VCC3 VDDQ NORTH BRIDGE VT82C694A/X-B DCLKWR R189 60 1% VDDQ Size Document Number R197 60 1% VT5228C (Prelimonary) MD[0..31]...
  • Page 125 R224 10K 1% V_BAT VBAT TSEN2 R301 103JT-025 CPUFAN1 CPUFAN1 FAN1 C168 CT49 R302 CPUFAN2 VIA TECHNOLOGIES, INC. FAN2/GPIOB/GPIO9 CPUFAN2 Place RT1 under CPU VCC3 VCC3 BAT1 Place RT2 near NB VCCHWM Title CB46 CT50 SOUTH BRIDGE VT82C686A-A GNDHWM Size...
  • Page 126 IRQ9 IRQ9 IRQ10 IRQ10 IRQ10 IRQ11 0 (OPT) IRQ11 IRQ11 IRQ14 IRQ14 IRQ14 IRQ15 IRQ15 IRQ15 SLP1 R200 XDIR/PCS0/GPO12 XOE/GPO13 VIA TECHNOLOGIES, INC. VCC3 Title SOUTH BRIDGE VT82C686A-B Size Document Number VT5228C (Prelimonary) VT82C686A-B Date: Wednesday, November 24, 1999 Sheet...
  • Page 127 74F273 C176 * Auto mode: Remove the BSEL0 and BSEL1 jumper, install JA jumper. * OPTION 1N4148 RST_SW -SERR C177 VIA TECHNOLOGIES, INC. NC7SZ125 For jumper-less circuit C178 Title USB2,3 / FREQ. RATIO Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999...
  • Page 128 WE2/DU MAA14 -SCASA -SCASA DU/A14 DU/CAS -SRASA -SRASA DU/A15 DU/RAS DIMM_16M*64 I2CD2 I2CD2 I2CD1 I2CD1 V_DIM V_DIM V_DIM CKE_2 CKE_3 DCLK1 DCLK2 DCLK3 DCLK4 VIA TECHNOLOGIES, INC. Title SDRAM Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999 Sheet...
  • Page 129 RING IN JWOL 5V_SB R343 WAKE_CONN MMBT3904 WAKE UP R327 5V_SB MMBT3904 R326 JWOM 100K C172 WAKE_CONN 1000p MODEM WAKE UP VIA TECHNOLOGIES, INC. Title SDRAM/LAN,MODEM WAKE UP FUNCTION Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999 Sheet...
  • Page 130 2.2K R182 RN21 -INTR_C 2.2K 2.2K -PERR -P1ACK64 -P1ACK64 -PLOCK R194 -FRAME 2.2K -IRDY VCC3 -P2ACK64 VIA TECHNOLOGIES, INC. -P2ACK64 4.7K 8P4R -INTR_B 2.2K Title -INTR_A 2.2K PCI SLOT Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999 Sheet...
  • Page 131 NDP6030L PGND VDDQ VREF_4X SC1105 C152 NDS8936 CT40 CT39 CT45 AGPVREF 1000u VIA TECHNOLOGIES, INC. BYV118 Title AGP SLOT & AGP 2X/4X MODE OPTION CIRCUIT Size Document Number VT5228C (Preliminary) For AGP 2X/4X mode Date: Wednesday, November 24, 1999 Sheet...
  • Page 132 IRQ10 R184 RN16 DREQ2 4.7K 4.7K 8P4R DREQ1 4.7K R114 C121 IRQ4 DREQ3 4.7K R102 IRQ5 IRQ6 R137 4.7K IRQ3 4.7K IRQ12 R195 VIA TECHNOLOGIES, INC. Title ISA SLOT Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999 Sheet...
  • Page 133 SA12 SDD12 SD_A2 SD_A1 R281 SDA1 SD_A1 SD_A0 R259 SDA0 R282 -DDACKB SD_A0 -DDACK_B R283 -DIOWB -DIOW_B R289 -DIORB VIA TECHNOLOGIES, INC. -DIOR_B R280 HDRDYB HDRDY_B PD_A2 R233 PDA2 R288 DDREQB PD_A2 DDREQ_B Title PD_A1 R237 PDA1 PD_A1 IDE/PANEL PD_A0...
  • Page 134 34.3MHz MS_CLK MS_CK MS_CLK 133MHz 33.3MHz 124MHz 31MHz 47pF 47pF 150MHz 37.5MHz VIA TECHNOLOGIES, INC. KEYBOARD WAKE UP 140MHz 35MHz *For ICS 9148-39/IC WORKS-144 Title CLOCK SYNTHESIZER/KB WAKE UP FUNCTION Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999...
  • Page 135 VCC3 CB15 CB18 CM19 CT34 CT37 C134 1500u 1000u CM39 CM38 CM42 CM26 CM32 CM33 CM27 CM25 CM20 CM21 CT48 1500u VDDQ CM28 CM31 CT38 CM35 CT44 CM34 CM37 CM36 1500U 1500u CT24 CM40 CM18 CM30 CM29 CM23 1500u VCCP V_DIM CM17 CM16...
  • Page 136 + C104 LT1587 1000u/6.3V C119 CM22 R122 1000u/6.3V 20 1% VCC2_5 VOUT R130 100 1% LT1587 + C105 1000u/6.3V R129 100 1% CM24 VIA TECHNOLOGIES, INC. Title DC-DC CONVERTER Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999 Sheet...
  • Page 137 P_PRD7 P_PRD7 P_PRD4 180PF 180PF 180PF 180PF P_PRD4 180PF 180PF 180PF 180PF 180PF 8P4R 33 P_ACK P_BUSY VIA TECHNOLOGIES, INC. P_PE 180PF 180PF 180PF 180PF 180PF 180PF 180PF P_SLCT 180PF Title PRINTER / COM PORT Size Document Number VT5228C (Preliminary)
  • Page 138 JBCY JACY JACY_ R351 0 (OPT) JACY JBB2 JBB2 JAB2 JAB2 R350 0 (OPT) VIA TECHNOLOGIES, INC. GND_LOUT GND_AUD GAME_PORT * For test audio quality Title 100p .01u AC97 AUDIO CODEC & AUDIO PORTS GND_MIDI Size Document Number VT5228C (Preliminary)
  • Page 139 SDIN SDIN AC97_SDATA_IN2 AC97_SDATA_IN0 R113 BITCLK R112 AC97_MSTRCLK AC97_BITCLK BITCLK_R 0 (OPT) AMR_SLOT AMR_AGND R108 R100 R106 10K (OPT) 10K (OPT) 10K (OPT) VIA TECHNOLOGIES, INC. Title AMR SLOT Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999 Sheet...
  • Page 140 CKE_4 R202 0 (OPT) CKE_5 C167 1u (OPT) R244 0 (OPT) R257 0 (OPT) R270 0 (OPT) PWRON -SUSC For NON-STR function VIA TECHNOLOGIES, INC. Title STR OPTION CIRCUIT Size Document Number VT5228C (Preliminary) Date: Wednesday, November 24, 1999 Sheet...

This manual is also suitable for:

Vt82c694x

Table of Contents