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2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines
2.4.1 Host CPU Interface Layout and Routing Guidelines
The GTL+ signals (host address bus, host data bus and host control signals) are typical point-to-point connections between CPU
and North Bridge in a Slot-1 or Socket-370 system design. VTT (1.5V) terminations are required for GTL+ signals. Except for
FERR#, all host control signals from the VT82C686A South Bridge to Slot-1 or Socket-370 CPU are open drain (OD) signals.
2.5V pull-ups are required for those open drain signals on the VT82C686A chip side. The routing topology for both signal groups
from VT82C694X and VT82C686A uses point-to-point connections. Recommended layout guidelines and routing examples for
GTL+ and OD signals are given in the following sections.
2.4.1.1 Slot-1 Host Interface to North Bridge
The recommended topology for Slot-1 host signals to the North Bridge (VT82C694X) is shown in Figure 2-33. For signal quality
considerations, the trace length of the host address bus should be minimized. No VTT terminations are required for a Slot-1
system since they are built in to both the Slot-1 CPU and the VT82C694X.
•
It is recommended to route all host signals to the VT82C694X in equal length and as short as possible. A minimum of 5
mils in width and a minimum of 10 mils in spacing are required for those host signals. The trace length of those signals
should be less than 4.5 inches.
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Total Trace Length (L) < 4.5"
VT82C694X
(North Bridge)
A[31..3]
D[63..0]
DBSY#
DRDY#
HIT#
HITM#
HREQ[4..0]#
HTRDY#
RS[2..0]#
BPRI#
BREQ0#
DEFER#
CPURST#
HLOCK#
Figure 2-33. Slot-1 Host Interface Topology Example
L
A[31..3]
D[63..0]
DBSY#
DRDY#
HIT#
HITM#
REQ[4..0]#
TRDY#
RS[2..0]#
BPRI#
BR0#
DEFER#
RESET#
LOCK#
41
Slot-1 CPU
Motherboard Design Guidelines
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