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We Connect
We Connect
The application circuit of the ultra DMA/66 IDE interface is shown in Figure 2-61. The 80-conductor cable, required by the ultra
DMA/66 IDE interface, is the major difference from the 40-conductor cable of the current IDE interface. For the detection of the
80-conductor cable, pin 34 (CBLID) of IDE connector may be used to provide a signal state from an ultra DMA/66 device to a
GPI pin of the South Bridge Controller. The detection can be done in an alternative hardware solution too.
Layout rules for the IDE interface in the former section can be adapted for ultra DMA/66 use unless some of them are modified in
the following layout guidelines.
•
The trace attribute of all primary IDE signals is in a minimum of 6 mils wide and 9 mils between two adjacent traces.
•
All signals for primary IDE and Secondary IDE require 33 ohm series termination resistors.
terminations as close (less than 1 inch) to the VT82C686A as possible.
•
Data and strobe lines should be routed as a bus. The total trace length of these signals should be shorter than 4.5 inches.
The maximum trace length difference among them must be less than 1 inch. Other lines should be as short as possible.
VT82C686A
(South Bridge)
PDDACK#
PDA[2..0]
DD[15..0]
PIORDY#
PDDREQ
Notes
1. 10K ohm resistor pull-down for DD7 only.
2. Pin 34 of primary IDE connector is connected to one of GPI pins from VT82C686A.
Preliminary Revision 0.5, November 19, 1999
R
A
33 ohm
F04
RSTDRV
PDIOW#
PDIOR#
PDCS1#
PDCS3#
10K ohm
(note 1)
Trace length (L2) < 3.5"
L2
IRQ14
GPI
(note 2)
Figure 2-61. Ultra DMA/66 Application Circuit
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Trace length (L1) < 3.5"
L1
R
B
33 ohm
470 ohm
69
Primary
IDE
Connector
1
IDERST#
23
IOW#
25
IOR#
29
DACK#
33
CS1#
38
CS3#
DA[2..0]
DD[15..0]
VCC
10K ohm
31
IRQ14
VCC
1K ohm
27
IORDY#
VCC
10K ohm
34
PDIAG#
21
DREQ
5.6K ohm
28
SPSYNC:CSEL
Motherboard Design Guidelines
Place these series
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