VIA Technologies Apollo Pro133A Design Manual page 125

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1
PD_D0
PD_D[0..15]
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
A
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_A0
PD_A0
PD_A1
PD_A1
PD_A2
PD_A2
-PDCS_1
-PDCS_1
-PDCS_3
-PDCS_3
-DDACK_A
-DDACK_A
DDREQ_A
DDREQ_A
-DIOR_A
-DIOR_A
-DIOW_A
-DIOW_A
HDRDY_A
HDRDY_A
A_D0
A_D[0..31]
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
B
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A_D16
A_D17
A_D18
A_D19
A_D20
A_D21
A_D22
A_D23
A_D24
A_D25
A_D26
A_D27
A_D28
A_D29
A_D30
A_D31
C_-BE0
C_-BE[0..3]
C_-BE1
C_-BE2
C_-BE3
C
-FRAME
-FRAME
-IRDY
-IRDY
-TRDY
-TRDY
-STOP
-STOP
-DEVSEL
-DEVSEL
-SERR
-SERR
PAR
PAR
A_D18
A_D18
-PCIREQ
-PCIREQ
-PCIGNT
-PCIGNT
-PCIRST
-PCIRST
-INTR_A
-INTR_A
-INTR_B
-INTR_B
-INTR_C
-INTR_C
-INTR_D
-INTR_D
SPCLK
SPCLK
CX2
10p
32.768KHz
VCC3_SB
CX1
10p
VCC3_SB
D8
1N5819
JBAT1
1
CB47
D6
1N5819
2
D
.1u
R301
3
1K
C168
CT49
R302
1K
.1u
10u
VCC3
BAT1
1
2
U20
P16
PDD0
SDD0/BITCLK
P18
PDD1
*SDD1/SDIN
P20
PDD2
*SDD2/SDIN2
R17
PDD3
SDD3/SYNC
R19
PDD4
SDD4/SDOUT
T16
PDD5
SDD5/-ACRST
T18
PDD6
SDD6/JBY
T20
PDD7
SDD7/JBX
T19
*:VSUS
PDD8
SDD8/JAY
T17
PDD9
SDD9/JAX
R20
PDD10
SDD10/JAB2
R18
PDD11
SDD11/JAB1
R16
PDD12
SDD12/JBB2
P19
PDD13
SDD13/JBB1
P17
PDD14
SDD14/MSO
N20
PDD15
SDD15/MSI
M17
PDA0
SDA0
M19
PDA1
SDA1
M18
PDA2
SDA2
L20
PDCS1
SDCS1
M16
PDCS3
SDCS3
M20
PDDACK
SDDACK
N19
PDDREQ
SDDREQ
N17
PDIOR
SDIOR
N18
PDIOW
SDIOW
N16
PDRDY
SDRDY
L17
AD0
L16
AD1
CPURST
K20
AD2
FERR
K19
AD3
IGNNE
K18
AD4
K17
AD5
K16
AD6
J20
AD7
SLP/GPO7
J18
AD8
J17
AD9
STPCLK
J16
AD10
H20
AD11
CPUSTP/GPO4
H19
AD12
PCISTP/GPO5
H18
AD13
H17
AD14
CLKRUN
H16
AD15
SPKR
F16
AD16
E20
AD17
GPIOA/GPIO8
E19
AD18
GPIOD
E18
AD19
E17
AD20
D20
AD21
*PWRGD
D19
AD22
*SMBCLK
D18
AD23
*SMBDATA
B20
AD24
A20
AD25
*GPO0
A19
AD26
*SUSST1/GPO6
B19
AD27
*SUSCLK
A18
AD28
B18
AD29
*EXTSMI
C18
AD30
*RING/GPI7
A17
AD31
*PME/GPI5/THRM
*BATLOW/GPI2
J19
C_BE0
*PWRBTN
G20
C_BE1
*RSMRST
F17
C_BE2
*GPI1/IRQ8
C19
C_BE3
*LID/APICREQ/GPI3
*SMBALT/GPI6
F18
FRAME
F19
IRDY
*SUSA/APICACK/GPO1
F20
TRDY
*SUSB/APICCS/GPO2
G17
STOP
*SUSC
G16
DEVSEL
G18
SERR
G19
PAR
C20
IDSEL
L18
REQ
L19
GNT
B16
PCIRST
A16
PINTA
D17
PINTB
C17
PINTC
B17
PINTD
E16
PCICLK
Y5
RTCX1
X3
CHAS/GPIOC/GPIO10
W5
RTCX2
TSEN1
R9
VCCSUS
R10
VCCSUS
V_BAT
Y6
VBAT
TSEN2
H15
VCC
J15
VCC
K15
VCC
FAN2/GPIOB/GPIO9
M15
VCC
N15
VCC
R7
VCC
VCCHWM
R8
VCC
R11
VCC
R14
VCC
GNDHWM
VT82C686A-A
2
W18
R57
22
BITCLK
V17
R105
22
SDIN
Y17
R99
22
SDIN2
V16
R264
22
SYNC
Y16
R265
22
SDOUT
U15
R266
22
-ACRST
W15
JBCY
JBCY
U14
JBCX
JBCX
Y15
JACY
JACY
V15
JACX
JACX
T15
JAB2
-CPUINIT
JAB2
W16
JAB1
JAB1
U16
JBB2
JBB2
W17
JBB1
-FERR
JBB1
Y18
MSO
MSO
Y19
MSI
MSI
-STPCLK
U19
SD_A0
SD_A0
V18
SD_A1
SD_A1
U20
SD_A2
-SMI
SD_A2
U17
-SDCS_1
-SDCS_1
U18
-SDCS_3
-SDCS_3
V19
-DDACK_B
-SLP
-DDACK_B
Y20
DDREQ_B
DDREQ_B
W19
-DIOR_B
-DIOR_B
W20
-DIOW_B
-DIOW_B
V20
HDRDY_B
HDRDY_B
Y7
-A20M_
A20M
-A20M_
V8
V7
-FERR
-FERR
Y8
-IGNNE_
-IGNNE_
T6
-CPUINIT
-CPUINIT
INIT
W8
INTR_
INTR_
INTR
U7
NMI_
NMI_
NMI
T7
-SLP
-SLP
U6
-SMI
-SMI
SMI
W7
-STPCLK
-STPCLK
VCC3
Y12
R267
10K
V12
R285
10K
W12
-CLKRUN
VCC3
V5
SPEAK_
T14
R263
10K
U8
R316
10K
GPIOD
W6
PW_GOOD
PW_GOOD
U9
I2CD1
I2CD1
T9
I2CD2
I2CD2
VCC3_SB
T8
R313
10K
V10
-SUSST
-SUSST
T10
SUS_CLK
Y10
-EXTSMI
-EXTSMI
V11
-RI
-RI
T11
-PME_
U11
-BATLOW
Y11
-PWRBTN
V6
-RSMRST
-RSMRST
W11
PD_80P
PD_80P
U10
SD_80P
SD_80P
W10
-SMBALT
V9
-SUSA
W9
-SUSB
-SUSB
Y9
-SUSC
-SUSC
+12V
F15
GND
VCC3
G15
GND
L15
GND
P15
VCC2_5
GND
R15
R290
GND
10K
VCCP
Y14
IN12
W14
IN5
U13
CM41
IN2A
V13
CM43
IN2B
V14
R291
W13
RT1
R121
10K 1%
T13
VREF
R224
10K 1%
Y13
RT2
T12
CPUFAN1
CPUFAN1
FAN1
U12
CPUFAN2
CPUFAN2
VCC3
R12
L34
FB
CB46
CT50
.1u
10u
R13
L35
FB
HM_GND
3
VCC2_5
-SUSST
R338
SUS_CLK
R311
R319
4.7K
-EXTSMI
R335
-BATLOW
R309
R342
4.7K
-SMBALT
R336
R341
4.7K
-SUSA
R310
-SUSB
R337
R320
4.7K
-RI
R304
R321
4.7K
PD_80P
R306
SD_80P
R312
I2CD1
R315
I2CD2
R314
VCC3_SB
R308
10K
R307
-PME_
0 (OPT)
VCC3_SB
R305
4.7K
R334
-PWRBTN
C174
68
.1u
R295
C170
R292
C169
53K 1%
16K 1%
.1u
.1u
R294
10K 1%
R293
10K 1%
1u
1u
SPEAK_
0(OPT)
L27
HM_GND
* Isolated from AMR,avoied strapping error.
103JT-025
L33
103JT-025
VIA TECHNOLOGIES, INC.
Place RT1 under CPU
Place RT2 near NB
Title
Size
C
Date:
3
4
VCC3
-A20M_
R340
4.7K
VCC3_SB
-IGNNE_
R318
4.7K
10K
INTR_
R317
4.7K
10K
NMI_
R339
4.7K
10K
-PCIGNT
R232
10K
10K
-PCIREQ
R235
10K
10K
10K
10K
-CLKRUN
R284
100
10K
10K
10K
4.7K
4.7K
J2
1
2
SDIN
SDIN_A
J1
1
BITCLK_A
2
BITCLK
3
4
-PME
BITCLK_R
J2
J1
AC97
1-2
1-2
MC97
OPEN
3-4
AC97
1-2
PW_BN
+
1-2
MC97
3-4
AMR
OPEN
3-4
J5
1
2
3
IRRX
IR
IRRX
4
5
IRTX
IRTX
VCC3
SPEAK_
R268
2K
NOTE: SECOND IDE BUS IS
ASSIGNED TO AUDIO/GAME
VCC3
2
4
SPEAK
U12
NC7SZ125
SOUTH BRIDGE VT82C686A-A
Document Number
VT5228C (Preliminary)
Wednesday, November 24, 1999
Sheet
5
of
20
4
A
B
C
D
Rev
0.1

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