Integrated Super Io Controller - VIA Technologies Apollo Pro133A Design Manual

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Voltage Monitoring
Typically VCC2 (core voltage of the CPU), VCCI (2.5V, core voltage of the VT82C694X), VCC3 (3.3V), 5V, and +12V are the
five monitored voltage inputs. VCC2 and VCCI can be directly connected to the inputs. The +5V and 12V inputs should be
attenuated with external resistors to any desired value within the input range. VCC3 is internally connected to the hardware
monitoring system voltage detection circuitry for 3.3V monitoring. An alarm will issue when any monitored voltage level is out of
range. Layout and grounding guidelines are listed below:
•
These voltage inputs will provide better accuracy when referred to their respective ground (GNDHWM) which is
separated from digital common ground (GND). Please refer to the application circuit above.
•
Voltage dividers should be located physically as close to the voltage input pins as possible.
Temperature Sensing
One internal thermal sensor is located inside the VT82C686A chip. Two external thermisters for two temperature sensing inputs
are used to directly contact the device whose temperature will be monitored. Layout and grounding guidelines are listed below:
•
The thermister should be placed very near a measured object. For example, a thermister can be placed right beside of a
Slot-1 CPU or under a Socket-370 CPU.
•
The other end of a thermister should be connected to ground through a ferrite bead.
Fan-Speed Monitoring
Fan speed inputs are provided for signals from fans equipped with tachometer outputs. One fan-speed-monitoring pin can be used
to measure the CPU fan speed. The other can be an auxiliary one. A programmable fan-speed control can be implemented in the
following three steps.
•
Speed Monitoring: The fan speed value is measured by a fan-speed monitoring pin
•
Temperature Sensing: The temperature value is measured by a temperature sensing pin
•
Speed Controlling: The fan speed is controlled by a dedicated General Purpose Output (GPO) pin
Chassis Intrusion Detection
The detection is an active high interrupt from any chassis intrusion violation. It could be accomplished mechanically, optically, or
electrically. Circuitry external to the chassis intrusion detect pin is expected to latch the event.

2.5.4 Integrated Super IO Controller

In the VT82C686A, an integrated Super IO Controller supports two UARTs for complete serial ports, one dedicated IR port, one
multi-mode parallel port, and one floppy drive controller function. Refer to the Apollo Pro-133 Reference Design Schematics in
Appendix C for more details on application circuits.
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
64 Motherboard Design Guidelines