VIA Technologies Apollo Pro133A Design Manual page 103

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We Connect We Connect
SDRAM Clock Trace Length Calculation
Pre-route SDRAM clock traces (SDCLK0~SDCLK15) from the system clock synthesizer to the DIMM slots as short as possible.
The length of all SDRAM clocks will be based on the longest one (L
that of the SDCLKs. The DCLKO clock trace should be as short as possible. A calculation example is shown below.
Clock Trace
Clock chip à SDCLK[15:0]
DCLKWR (Clock chip à NB)
DCLKO (NB à Clock chip)
Note: Here, the 4.5" represents the estimated trace length added into DCLKI for SDRAM clock alignment.
AGP Clock Trace Length Calculation
Pre-route AGP clock traces from the pin GCLKO of the VT82C694X to the AGP slot as short as possible. Then the trace length
for the signal GCLK should be the GCLKO trace length plus 3 inches.
Clock Trace
GCLKOUT (NB à AGP Slot)
GCLKIN (NB à NB)
Note: Here, the 3" represents the estimated trace length added into GCLKI for AGP clock alignment.
PCI Clock Trace Length Calculation
Pre-route PCI clock traces from the system clock synthesizer to the VT82C694X (NPCLK) and VT82C686A (SPCLK) as short as
possible. Then pre-route PCI clock traces PCLK0~PCLK4 from the system clock synthesizer to all PCI slots as short as possible.
The length of these clocks will be based on the longest one (L
Clock Trace
Clock chip à VT82C694X (NB)
Clock chip à VT82C686A (SB)
Clock chip à PCI1
Clock chip à PCI2
Clock chip à PCI3
Clock chip à PCI4
Clock chip à PCI5
Note: Here, the 3" represents the estimated trace length added into NPCLK and SPCLK for PCI clock alignment.
Notes for the length calculation of all clock traces:
1. Shortest length means the minimum routable trace length between both clock ends. Desired length means the real length of the
clock traces on PCB layout. Allowable difference means the maximum difference between clock traces of the same type.
Allowable range means the acceptable clock length range for the specific clock.
2. The location of the system clock chip can affect the length of all clock traces. To optimize the clock alignment, place the clock
chip at an appropriate location.
3. In addition, the trace impedance of all clock traces should be in the range between 40 ohms and 55 ohms.
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
SD
Shortest
Length
L
SD
L (assume < L +3")
DIN SD
L
DOUT
Shortest
Length
L
GOUT
L
GIN
). A calculation example is shown below.
5
Shortest
Length
L
NB
L
SB
L
1
L
2
L
3
L
4
L ( > the others)
5
93
). The length of DCLKWR (L
Desired Allowable
Length Difference
L 0.5"
SD
0.5"
L + 4.5"
SD
-
L
DOUT
Desired Allowable
Length Difference
L -
GOUT
L + 3" 0.5"
GOUT
Desired Allowable
Length Difference
1"
L + 3"
5
L + 3" 1"
5
L 1"
5
1"
L
5
1"
L
5
1"
L
5
L -
5
Signal Connectivity and Design Checklist
) should be the same as
DIN
Allowable
Range
1"~4"
5.5"~8.5"
1"~9"
Allowable
Range
1"~9"
4"~12"
Allowable
Range
4"~15"
4"~15"
1"~12"
1"~12"
1"~12"
1"~12"
1"~12"