Timing Analysis And Simulation; Sdram Timing; Figure 3-1. Cpu Read From Sdram (Sl=2) - VIA Technologies Apollo Pro133A Design Manual

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The 133 MHz timing analysis here will provide a basis for the concept of trace length limitation for some high speed buses and
control signals such as the CPU address bus (A[31:3]). A brief analysis is given for each diagram. 133 MHz system frequency is
assumed where one clock (1T) represents 7.5 ns. Reasons for the limited lengths of some signals (referring to Section 2.3) are
described in the timing analyses.

3.1 SDRAM Timing

Timing diagrams for CPU Read from SDRAM and CPU Post Write to SDRAM are illustrated in Figures 3-1 and 3-2. Timing
analyses for SDRAM read and write cycles are listed below:
•
The clock skew between the CPU clock and the SDRAM clocks will affect the setup time and hold time of SDRAM
command signals and MD[63..0] because the CPU reads or writes the data out of or into the SDRAM. Therefore, clock
alignment between the CPU clock and the SDRAM clocks should be maintained.
•
According to the cycles below, the timing is critical. In order to increase the timing margin of the cycle, one of the best
solutions is to minimize the propagation delay of the MD[63..0] and SDRAM control signals on the PCB. Therefore, the
length of MD[63..0] and the SDRAM control signals should be limited because there is only one clock between assertion
of the SDRAM control signals and data input or output.
CCLK
ADS#
HREQ#
HA#
RS#
DBSY#
DRDY#
HTRDY#
HD
CS#
SRAS#
SCAS#
SWE#
MD#
Consideration:
A: Be careful of the MD data length
B: Be careful of the CPU data length
C: Be careful of the CPU address length
D: Be careful of the CPU control signal length
Preliminary Revision 0.5, November 19, 1999
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IMING NALYSIS AND
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Figure 3-1. CPU Read from SDRAM (SL=2)

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
S
IMULATION
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Timing Analysis and Simulation