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2.4.2 Memory Subsystem Layout and Routing Guidelines
2.4.2.1 DRAM Routing Guidelines
Most DRAM signals are multi-drop connections. A brief description of the memory subsystem signals is provided in Table 2-10
below.
Signal Name
MAA[14:0]
MAB[14:11]#, MAB10, MAB[9:0]#
MD[63:0]
MECC[7:0]
RASA[5:0]#
RASB[5:0]#
CASA[7:0]#
CASB5#, CASB1#
SRASA#
SRASB#
SCASA#
SCASB#
SWEA#
SWEB#
Note: Group A represents the first two DIMM modules and group B represents the remaining (one or two) modules. CASA[7:6,
4:2, 0]# can also be connected to the DIMM modules of group B.
The maximum DRAM installation is four DIMM slots. Three layout examples (Daisy Chain Ordering) for all DRAM buses and
control signals between the Apollo Pro133A North Bridge and four, three or two DRAM DIMM slots are shown in Figure 2-39, 2-
40 and 2-42 respectively. One T-Style layout example for DRAM signals, such as MD[63:0] and MECC[7:0], between the Apollo
Pro133A North Bridge and three DRAM DIMM slots is shown in Figure 2-41. Routing recommendations for the DRAM interface
are listed below.
•
Traces for all DRAM signals should be a minimum of 5 mils in width and 10 mils in spacing. The accumulated trace
length for all signals should be under 4 inches to meet 133 MHz timing requirements. The length difference among traces
should be minimized.
•
The DRAM interface damping resistors are no longer needed.
•
For daisy chain routing, traces of MD[63:0], CASA[7:0]# and MECC[7:0] should be connected to the DIMM modules in
order of DIMM4, DIMM3, DIMM2 and DIMM1 (see Figure 2-39).
VT82C694X chip.
•
It is recommended to make segments L2, L3 and L4 as short as possible in Figure 2-39.
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Table 2-10. Memory Subsystem Signals
North Bridge -- DRAM
I/O
O
Memory Address for the group A
O
Memory Address for the group B
IO
Memory Data for all four DIMM modules
IO
DRAM ECC or EC Data for all four DIMM modules
O
Row Address Strobe of each bank
O
Row Address Strobe of each bank
O
Column Address Strobe of each byte lane for the group A
O
Column Address Strobe of each byte lane for the group B
O
Row Address Command Indicator for the group A
O
Row Address Command Indicator for the group B
O
Column Address Command Indicator for the group A
O
Column Address Command Indicator for the group B
O
Write Enable Command Indicator for the group A
O
Write Enable Command Indicator for the group B
46
Description
DIMM4 is the closest DIMM slot to the
Motherboard Design Guidelines
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