Vt82C694X Power Up Strappings; Vt82C686A Power Up Strappings; Table 2-4. Power-Up Configuration For Vt82C694X; Table 2-5. Power-Up Configuration For Vt82C686A - VIA Technologies Apollo Pro133A Design Manual

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2.2.8.1 VT82C694X Power Up Strappings

Internal configuration registers of Apollo Pro133A digital core logic are based on the status of memory address lines
(MAB[12:11]#, MAB10, MAB[9:6]#) and Host address lines (A15# and A7#). These memory address signals are pulled up or
pulled down with internal resistors on their I/O buffers to determine the default configurations. If the default configuration setting
is acceptable, no external pulled down resistors are necessary. However, the existence of an external pull-up or pull-down will
insure that the correct configuration is detected. These memory address signals may be pulled up or pulled down with external
resistors to determine the desired configurations. Please refer to Table 2-4 for the power up configuration of all strapping signals.
Signal Name Pin #
MAB12# AD21 CPU Bus Frequency Select: 0 = 66MHz, 1 = 100MHz
MAB11# AE21 In Order Queue Depth (IOQD) Enable:
0 = Non-Pipelined, 1 = Maximum Queue Depth Enabled
MAB10 AB20 Quick Start Select (Mobile only):
0 = Enable Standard Stop Clock Mode, 1 = Enable Quick Start Mode
MAB9# AC20 AGP Enable: 0 = Enable AGP Function,
MAB8# AF20 CPU Frequency Select 1: 0 = 66/100MHz, 1 = 133MHz
MAB7# AB19 Memory Module Configuration:
MAB6# AB18 Mobile Buffers Enable: 0 = Use Desktop Buffers, 1 = Use Mobile Buffers
A15# E22 Quick Start Select (Mobile only):
0 = Enable Quick Start Mode, 1 = Enable Standard Stop Clock Mode
A7# G24 IOQD Status: 0 = 1, 1 = IOQD set to Maximum
Notes:
1. "0" represents the logical state is "low". An external or internal pull-down resistor is required. Conversely, "1" represents the
logical state is "high". An external or internal pull-up resistor is required.
2. MAB11# is connected to an internal 100K ohm pull-up resistor. MAB12#, MAB10, MAB[9:6]# are connected to internal 100K
ohm pull-down resistors.
3. The A15# and A7# are terminated on the CPU bus with GTL+ termination (pull-up resistors).

2.2.8.2 VT82C686A Power Up Strappings

The power up configuration for the VT82C686A South Bridge is shown in Table 2-5 below. The strapping of SPKR (pin V5 of
the VT82C686A) is sampled during reset to determine the usage of the Secondary Disk Data (SDD) pins. When connecting the
SPKR signal to a speaker, the strapping circuit of SPKR is slightly different from the regular strapping circuit. Two application
circuits for SPKR strapping are shown in Appendix A.
Signal Name Pin #
SPKR V5 Selection for Secondary IDE data bus or Audio/GAME function:
1 = Audio/GAME (Audio/Game uses SDD bus and SA[15:0] can also function as SDD bus).
0 = Secondary IDE data bus (Primary IDE and Secondary IDE have their own data buses).
ROMCS# C1 Selection of Socket-7 configuration or Slot-1 configuration:
1 = Slot-1 for Pentium II or Socket-370 (also called "Socket-9") for Celeron
0 = Socket-7
Note:
1. " 0" represents the logical state is "low". An external or internal pull-down resistor is required. Conversely, " 1" represent
the local state is " high". An external or internal pull-up resistor is required.
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A

Table 2-4. Power-Up Configuration for VT82C694X

Table 2-5. Power-Up Configuration for VT82C686A

Strapping Description
1 = Disable AGP Function
Strapping Description
28
Note
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,3
1,3
Note
1
1
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