Clock Trace Checklist; Clock Trace Length Calculation - VIA Technologies Apollo Pro133A Design Manual

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5.4.4 Clock Trace Checklist

The general clock routing guidelines are listed below:
•
The recommended range of a clock trace width is between 15 mils and 20 mils.
•
The minimum space between one clock trace and adjacent clock traces is 15 mils. The minimum space from one segment
of a clock trace to other segments of the same clock trace is two times of the clock width. That is, more space is needed
from one clock trace to others or its own trace to avoid signal coupling.
•
Clock traces should be parallel to their reference ground planes. That is, a clock trace should be right beneath or on top of
its reference ground plane.
•
Series terminations (damping resistors) are needed for all clock signals (typically 10 ohms to 33 ohms). When two loads
are driven by one clock signal, separate series terminations are required. When multiple loads (more than two) are
applied, a clock buffer solution is preferred.
•
Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels (typically 20 mils to 50
mils) are preferred.
•
No clock traces on the internal layer if a six-layer board is used.

5.4.5 Clock Trace Length Calculation

The trace length calculations for different clock signal groups are described in this section. A different component placement may
result in a different calculation for the clock trace length. The trace length of those clock signals not mentioned in this section
should be as short as possible or less than 9 inches.
CPU Clock Trace Length Calculation for Slot-1 System
Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Slot-1
CPU (CPUCLK) and North Bridge (HCLK) as short as possible. All high frequency clock alignment will be on the basis of the
longest one (usually CPUCLK). A calculation example is shown below.
Clock Trace
Clock chip à CPU
Clock chip à VT82C694X (NB)
Note: Here, the 3" represents the estimated trace length added into HCLK for CPU clock alignment.
CPU Clock Trace Length Calculation for Socket-370 System
Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Socket-
370 CPU (CPUCLK) and North Bridge (HCLK) as short as possible. All high frequency clock alignment will be on the basis of
the longest one (usually HCLK). A calculation example is shown below.
Clock Trace
Clock chip à CPU
Clock chip à VT82C694X (NB)
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
Shortest Desired
Length Length
L
L
CPU CPU
L
L
NB CPU
Shortest Desired
Length Length
L L
CPU
NB
L L
NB
NB
92
Allowable Allowable
Difference
-
0.5" 4"~12"
+ 3"
Allowable Allowable
Difference
0.5"
-
Signal Connectivity and Design Checklist
Range
1"~9"
Range
1"~9"
1"~9"