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Design Guide - VT82C694X Apollo Pro133 with VT82C686A
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Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge ............................................................ 4
Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View) ............................................................ 7
Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View)................................................ 8
Figure 2-3. ATX Placement and Routing Example for Slot-1 System........................................................................................... 10
Figure 2-4. Micro-ATX Placement and Routing Example for Slot-1 System ................................................................................ 11
Figure 2-5. ATX Placement and Routing Example for Socket-370 System................................................................................... 13
Figure 2-6. Micro-ATX Placement and Routing Example for Socket-370 System ........................................................................ 14
Figure 2-7. Four-Layer Stack-up with 2 Signal Layers and 2 Power Planes ............................................................................... 15
Figure 2-8. Six-Layer Stack-up with 4 Signal Layers and 2 Power Planes .................................................................................. 16
Figure 2-9. Example of Via Location ......................................................................................................................................... 17
Figure 2-10. Decoupling Capacitor Placement for Single Slot-1 Processor................................................................................ 18
Figure 2-11. Decoupling Capacitor Placement for Single Socket-370 Processor ........................................................................ 19
Figure 2-12. Decoupling Capacitor Placements for VT82C694X and VT82C686A ..................................................................... 20
Figure 2-13. Decoupling Capacitor Placements for DRAM Modules.......................................................................................... 20
Figure 2-14. ATX Power Plane Partitions for Slot-1 System....................................................................................................... 21
Figure 2-15. Micro-ATX Power Plane Partitions for Slot-1 System ............................................................................................ 22
Figure 2-16. ATX Power Plane Partitions for Socket-370 System............................................................................................... 23
Figure 2-17. Micro-ATX Power Plane Partitions for Socket-370 System .................................................................................... 24
Figure 2-18. VT82C694X Power and Ground Layout ................................................................................................................ 25
Figure 2-19. VT82C686A Power and Ground Layout ................................................................................................................ 26
Figure 2-20. A Typical Example of a 3-pin Jumper Strapping Circuit......................................................................................... 27
Figure 2-21. System Clock Connections..................................................................................................................................... 30
Figure 2-22. Apollo Pro133A Chip Clocking Scheme................................................................................................................. 31
Figure 2-23. Clock Trace Spacing Guidelines............................................................................................................................ 32
Figure 2-24. Effect of Ground Plane to a Clock Signal .............................................................................................................. 32
Figure 2-25. Series Termination for Multiple Clock Loads......................................................................................................... 32
Figure 2-26. Host Clock and SDRAM Clock Layout Recommendations for Slot-1 System ........................................................... 34
Figure 2-27. Host Clock and SDRAM Clock Layout Recommendations for Socket-370 Systems.................................................. 35
Figure 2-28. AGP Clock Layout Recommendations.................................................................................................................... 36
Figure 2-29. PCI Clock Layout Recommendations..................................................................................................................... 37
Figure 2-30. Daisy Chain Routing Example............................................................................................................................... 40
Figure 2-31. Point-to-Point and Multi-Drop Topology Examples ............................................................................................... 40
Figure 2-32. Alternate Multi-Drop Topology Example............................................................................................................... 40
Figure 2-33. Slot-1 Host Interface Topology Example................................................................................................................ 41
Figure 2-34. Socket-370 Host Interface Topology Example........................................................................................................ 42
Figure 2-35. Host Interface Layout Example between Socket-370 and VT82C694X .................................................................... 43
Figure 2-36. Schematic Example for Slot-1 CPU Internal/External Clock Ratio Pin Sharing....................................................... 44
Figure 2-37. Layout Example of Control Signal from South Bridge to Slot-1 CPU...................................................................... 45
Figure 2-38. Layout Example of Control Signal from South Bridge to Socket-370 CPU.............................................................. 45
Figure 2-39. Daisy Chain Routing for Four-DRAM DIMM Slots................................................................................................ 47
Figure 2-40. Daisy Chain Routing for Three-DRAM DIMM Slots .............................................................................................. 48
Figure 2-41. T-Style Routing for Three-DRAM DIMM Slots....................................................................................................... 49
Figure 2-42. Daisy Chain Routing for Two-DRAM DIMM Slots................................................................................................. 50
Figure 2-43. DRAM Placement for 133MHz Timing Consideration............................................................................................ 50
Figure 2-44. Layout Example of Three-DRAM DIMM Slots ....................................................................................................... 51
Figure 2-45. General Layout Recommendations of AGP 4X Interface ........................................................................................ 52
Figure 2-46. AGP 2X and 4X Mode Sharing Circuit .................................................................................................................. 53
Figure 2-47. VDDQ Voltage-Switching Application Circuit ....................................................................................................... 54
Figure 2-48. VDDQ Voltage-Switching Application Circuit (II) ................................................................................................. 54
Figure 2-49. AGP VDDQ Power Plane Partition Example......................................................................................................... 55
Figure 2-50. AGP 4X Interface Layout Example ......................................................................................................................... 57
Figure 2-51. Topology Example of AGP and PCI Interface......................................................................................................... 58
Figure 2-52. USB Over-Current Scan Logic .............................................................................................................................. 59
Figure 2-53. USB Differential Signal Routing Example .............................................................................................................. 60
Preliminary Revision 0.5, November 19, 1999
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