Host Cpu Clock And Sdram Clock Signals; Figure 2-26. Host Clock And Sdram Clock Layout Recommendations For Slot-1 System - VIA Technologies Apollo Pro133A Design Manual

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2.3.2.5 Host CPU Clock and SDRAM Clock Signals

Layout recommendations for host clocks and SDRAM clocks for Slot-1 and Socket-370 CPUs are shown in Figure 2-26 and 2-27
respectively. 22 ohm and 10 ohm series terminations are recommended for all host clocks and all SDRAM clocks respectively. It
is also recommended that bypass capacitors be added to all clock signals on the clock synthesizer side. Different values of series
terminations and bypass capacitors are needed for a better clock transmission and alignment on the final PCB layout. In other
words, it is best to observe the actual clock waveform and experimentally determine the optimal values for series termination and
bypass capacitors. For clock alignment considerations, trace lengths of all clocks should match the longest one.
CPUCLK
SDCLKIN
SDCLK_F
System
Clock
Synthesizer
SDCLK0
SDCLK1
SDCLK2
SDCLK3
SDCLK4
SDCLK5
SDCLK6
SDCLK7
SDCLK8
SDCLK9
SDCLK10
SDCLK11
SDCLK12
SDCLK13
SDCLK14
SDCLK15

Figure 2-26. Host Clock and SDRAM Clock Layout Recommendations for Slot-1 System

Preliminary Revision 0.5, November 19, 1999
0 ~ 33
10 ~ 33 pF
ohm
HCLK
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
L
CPU
L + 3"
CPU
L
DOUT
(as short as possible)
L + 4.5"
SD
L
SD
L
SD
L
SD
L
SD
34
Slot-1 CPU
VT82C694X
HCLK
0 ~ 33
ohm
DCLKO
10 ~ 33 pF
(near the chip)
DCLKWR
10 ~ 33 pF
(near the chip)
DIMM1
CK0
CK1
CK2
CK3
DIMM2
CK0
CK1
CK2
CK3
DIMM3
CK0
CK1
CK2
CK3
DIMM4
CK0
CK1
CK2
CK3
Motherboard Design Guidelines