Pci Interface Layout And Routing Guidelines; Figure 2-51. Topology Example Of Agp And Pci Interface - VIA Technologies Apollo Pro133A Design Manual

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2.4.4 PCI Interface Layout and Routing Guidelines

It is recommended that the VT82C694X and VT82C686A be placed at both ends of the PCI bus for better signal termination. A
topology example of the AGP and PCI buses on an ATX form factor is shown in Figure 2-51 below. PCI signal traces may be
placed on either the component layer or the solder layer. Most AGP signal traces should be placed on the component layer.
Each of the following signals IRDY#, TRDY#, DEVSEL#, STOP#, LOCK#, PERR#, SERR#, FRAME#, INTA#, INTB#, INTC#,
and INTD# for the PCI interface requires a 4.7K ohm pull-up to VCC5. The REQ# signals need 2.2K ohm pull-ups to VCC5. The
GNT# signals need 2.2K ohm pull-ups to VCC3.
The layout guidelines for PCI signals are listed below:
•
Maintain 5 mil trace width and 10 mil clearance to its adjacent signals.
•
Route to minimum trace length wherever possible.
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
VT82C686A
South Bridge

Figure 2-51. Topology Example of AGP and PCI Interface

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VT82C694X
North Bridge
Motherboard Design Guidelines