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2.3.2.7 PCI Clock Signals
Layout recommendations for the PCI clocks are shown in Figure 2-29. Typically, 22 ohm series terminations are recommended
for all PCI clocks. A typical 22 pF bypass capacitor is also required for each PCI clock. Depending on how the system is
designed, the value of the bypass capacitors for the PCI clocks may vary. For clock alignment considerations, trace lengths of all
PCI clocks should match the longest one.
System
Clock
Synthesizer
2.3.2.8 Miscellaneous Clock Signals
22 ohm series terminations are recommended for clock signals such as the USB clock (48 MHz), Super I/O clock (typically 24
MHz), IOAPIC clock (14.31818MHz, 2.5V interface) and reference clock (14.31818 MHz, 3.3V interface) which are generated
from the system clock synthesizer. The trace width for the clocks above should be at least 15 mils. To reduce crosstalk impact,
trace spacing between these clocks and other signals should be maintained at a minimum of 15 mils. In order to maintain the
clock signal quality, the trace length of these clock signals, especially USBCLK, should be as short as possible or less than 9
inches.
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
0 ~ 33
10 ~ 33
ohm
NPCLK
SPCLK
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
Figure 2-29. PCI Clock Layout Recommendations
37
L
+ 3" (L
)
pF
5
NB
L
+ 3" ( L
)
5
SB
L
( L
)
5
1
L
( L
)
5
2
L
( L
)
5
3
L
( L
)
5
4
L
5
( Assume L
> L
, L
5
1
2
VT82C694X
(North Bridge)
VT82C686A
(South Bridge)
P
C
I
1
P
C
I
2
P
C
I
3
P
C
I
4
P
C
I
and the rest )
5
Motherboard Design Guidelines
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