Figure 3-2. Cpu Post Write To Sdram (Sl=2) - VIA Technologies Apollo Pro133A Design Manual

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CCLK
ADS#
HREQ#
HA#
RS#
DBSY#
DRDY#
HTRDY#
HD
CS#
SRAS#
SCAS#
SWE#
DQM#
MD#
Consideration:
A: Be careful of the MD data length
B: Be careful of the CPU data length
C: Be careful of the CPU address length
D: Be careful of the CPU control signal length
Preliminary Revision 0.5, November 19, 1999
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Figure 3-2. CPU Post Write to SDRAM (SL=2)

Design Guide - VT82C694X Apollo Pro133 with VT82C686A
74 Timing Analysis and Simulation