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2.3.2.6 AGP Clock Signals............................................................................................................................................. 36
2.3.2.7 PCI Clock Signals .............................................................................................................................................. 37
2.3.2.8 Miscellaneous Clock Signals .............................................................................................................................. 37
2.3.2.9 Clock Trace Length Calculation.......................................................................................................................... 38
2.3.3 Routing Styles and Topology..................................................................................................................................... 40
2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines ....................................................................41
2.4.1 Host CPU Interface Layout and Routing Guidelines .................................................................................................. 41
2.4.1.1 Slot-1 Host Interface to North Bridge.................................................................................................................. 41
2.4.1.2 Socket-370 Host Interface to North Bridge.......................................................................................................... 42
2.4.1.3 CPU Host Interface to South Bridge ................................................................................................................... 44
2.4.2 Memory Subsystem Layout and Routing Guidelines.................................................................................................. 46
2.4.2.1 DRAM Routing Guidelines ................................................................................................................................ 46
2.4.2.2 DRAM Reference Layout ................................................................................................................................... 50
2.4.3 AGP (4X Mode) Interface Layout and Routing Guidelines ........................................................................................ 52
2.4.3.1 General Layout and Routing Recommendations.................................................................................................. 52
2.4.3.2 Vref Characteristics for AGP 4X Mode............................................................................................................... 53
2.4.3.3 AGP VDDQ Power Delivery .............................................................................................................................. 53
2.4.3.4 AGP VDDQ Power Plane Partition..................................................................................................................... 55
2.4.3.5 Optimized Layout and Routing Recommendations.............................................................................................. 56
2.4.4 PCI Interface Layout and Routing Guidelines ............................................................................................................ 58
2.5 Super South (VT82C686A) Layout and Routing Guidelines .......................................................................59
2.5.1 USB controller.......................................................................................................................................................... 59
2.5.2 AC'97 Link and Game/MIDI Ports............................................................................................................................ 61
2.5.2.1 AC'97 Link ........................................................................................................................................................ 61
2.5.2.2 Game/MIDI ports ............................................................................................................................................... 62
2.5.3 Hardware Monitoring................................................................................................................................................ 63
2.5.4 Integrated Super IO Controller .................................................................................................................................. 64
2.5.5 System Management Bus Interface............................................................................................................................ 65
2.5.6 IDE........................................................................................................................................................................... 66
2.5.7 Suspend to DRM....................................................................................................................................................... 70
2.5.7.1 Suspend DRAM Refresh .................................................................................................................................... 70
2.5.7.2 STR Power Plane Control................................................................................................................................... 71
Timing Analysis and Simulation ................................................................................................................ 73
3.1 SDRAM Timing.............................................................................................................................................73
Electrical Specifications............................................................................................................................. 75
4.1 Absolute Maximum Ratings..........................................................................................................................75
4.2 Recommended Operating Ranges .................................................................................................................75
4.3 DC Characteristics ........................................................................................................................................76
4.4 Power Dissipation ..........................................................................................................................................76
Signal Connectivity and Design Checklist.................................................................................................. 77
5.1 Overview ........................................................................................................................................................77
5.2 VT82C694X Apollo Pro133A North Bridge .................................................................................................78
5.3 "Super South" South Bridge Controller.......................................................................................................81
5.4 Apollo Pro-133A Design Checklist ................................................................................................................90
5.4.1 General Layout Considerations Checklist .................................................................................................................. 90
5.4.2 Major Components Checklist .................................................................................................................................... 90
5.4.3 Decoupling Recommendations Checklist................................................................................................................... 91
5.4.4 Clock Trace Checklist ............................................................................................................................................... 92
5.4.5 Clock Trace Length Calculation ................................................................................................................................ 92
Preliminary Revision 0.5, November 19, 1999
Design Guide - VT82C694X Apollo Pro133 with VT82C686A
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