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Instruction
Group
16-bit
operation
Multiply/
divide
Increment/
decrement
Rotate
BCD
adjustment
Bit
manipulate
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
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Mnemonic
Operands
ADDW
AX, #word
SUBW
AX, #word
CMPW
AX, #word
MULU
X
DIVUW
C
INC
r
saddr
DEC
r
saddr
INCW
rp
DECW
rp
ROR
A, 1
ROL
A, 1
RORC
A, 1
ROLC
A, 1
ROR4
[HL]
ROL4
[HL]
ADJBA
ADJBS
MOV1
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
When an area except the internal high-speed RAM area is accessed
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 21 INSTRUCTION SET
Clocks
Bytes
Note 1
Note 2
−
AX, CY ← AX + word
3
6
−
AX, CY ← AX − word
3
6
−
AX − word
3
6
−
AX ← A × X
2
16
−
AX (Quotient), C (Remainder) ← AX ÷ C
2
25
−
r ← r + 1
1
2
(saddr) ← (saddr) + 1
2
4
6
−
r ← r − 1
1
2
(saddr) ← (saddr) − 1
2
4
6
−
rp ← rp + 1
1
4
−
rp ← rp − 1
1
4
−
1
2
(CY, A
−
1
2
(CY, A
−
(CY ← A
1
2
−
(CY ← A
1
2
2
10
12
A
3 − 0
(HL)
2
10
12
A
3 − 0
(HL)
−
2
4
Decimal Adjust Accumulator after Addition
−
2
4
Decimal Adjust Accumulator after Subtract
CY ← (saddr.bit)
3
6
7
−
CY ← sfr.bit
3
7
−
CY ← A.bit
2
4
−
CY ← PSW.bit
3
7
CY ← (HL).bit
2
6
7
(saddr.bit) ← CY
3
6
8
−
sfr.bit ← CY
3
8
−
A.bit ← CY
2
4
−
PSW.bit ← CY
3
8
(HL).bit ← CY
2
6
8
Preliminary User's Manual U19014EJ1V0UD
Operation
← A
← A
) × 1 time
, A
m − 1
7
0
m
← A
← A
) × 1 time
, A
0
7
m + 1
m
← CY, A
← A
) × 1 time
, A
m − 1
0
7
m
← CY, A
← A
) × 1 time
, A
7
0
m + 1
m
← (HL)
← A
, (HL)
,
3 − 0
7 − 4
3 − 0
← (HL)
3 − 0
7 − 4
← (HL)
← A
, (HL)
,
7 − 4
3 − 0
3 − 0
← (HL)
7 − 4
3 − 0
) selected by the processor clock
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
479
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