NEC mPD78F0730 Preliminary User's Manual page 478

Instruction
Mnemonic
Group
8-bit OR
operation
XOR
CMP
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
2. This clock cycle applies to the internal ROM program.
478
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CHAPTER 21 INSTRUCTION SET
Operands
A, #byte
saddr, #byte
Note 3
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
Note 3
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
Note 3
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
control register (PCC).
Preliminary User's Manual U19014EJ1V0UD
Clocks
Bytes
Note 1 Note 2
− A ← A ∨ byte
2 4
(saddr) ← (saddr) ∨ byte
3 6 8
− A ← A ∨ r
2 4
− r ← r ∨ A
2 4
A ← A ∨ (saddr)
2 4 5
A ← A ∨ (addr16)
3 8 9
A ← A ∨ (HL)
1 4 5
A ← A ∨ (HL + byte)
2 8 9
A ← A ∨ (HL + B)
2 8 9
A ← A ∨ (HL + C)
2 8 9
− A ← A ∨ byte
2 4
(saddr) ← (saddr) ∨ byte
3 6 8
− A ← A ∨ r
2 4
− r ← r ∨ A
2 4
A ← A ∨ (saddr)
2 4 5
A ← A ∨ (addr16)
3 8 9
A ← A ∨ (HL)
1 4 5
A ← A ∨ (HL + byte)
2 8 9
A ← A ∨ (HL + B)
2 8 9
A ← A ∨ (HL + C)
2 8 9
− A − byte
2 4
(saddr) − byte
3 6 8
− A − r
2 4
− r − A
2 4
A − (saddr)
2 4 5
A − (addr16)
3 8 9
A − (HL)
1 4 5
A − (HL + byte)
2 8 9
A − (HL + B)
2 8 9
A − (HL + C)
2 8 9
Operation
) selected by the processor clock
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×