Table of Contents
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Instruction
Mnemonic
Group
Conditional
BT
branch
BF
BTCLR
DBNZ
CPU
SEL
control
NOP
EI
DI
HALT
STOP
Notes 1.
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
2. This clock cycle applies to the internal ROM program.
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CHAPTER 21 INSTRUCTION SET
Operands
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
RBn
control register (PCC).
Preliminary User's Manual U19014EJ1V0UD
Clocks
Bytes
Note 1
Note 2
PC ← PC + 3 + jdisp8 if (saddr.bit) = 1
3
8
9
−
PC ← PC + 4 + jdisp8 if sfr.bit = 1
4
11
−
PC ← PC + 3 + jdisp8 if A.bit = 1
3
8
−
PC ← PC + 3 + jdisp8 if PSW.bit = 1
3
9
PC ← PC + 3 + jdisp8 if (HL).bit = 1
3
10
11
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
4
10
11
−
PC ← PC + 4 + jdisp8 if sfr.bit = 0
4
11
−
PC ← PC + 3 + jdisp8 if A.bit = 0
3
8
−
PC ← PC + 4 + jdisp8 if PSW. bit = 0
4
11
PC ← PC + 3 + jdisp8 if (HL).bit = 0
3
10
11
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
4
10
12
then reset (saddr.bit)
PC ← PC + 4 + jdisp8 if sfr.bit = 1
−
4
12
then reset sfr.bit
−
PC ← PC + 3 + jdisp8 if A.bit = 1
3
8
then reset A.bit
−
PC ← PC + 4 + jdisp8 if PSW.bit = 1
4
12
then reset PSW.bit
PC ← PC + 3 + jdisp8 if (HL).bit = 1
3
10
12
then reset (HL).bit
−
B ← B − 1, then
2
6
PC ← PC + 2 + jdisp8 if B ≠ 0
−
C ← C −1, then
2
6
PC ← PC + 2 + jdisp8 if C ≠ 0
(saddr) ← (saddr) − 1, then
3
8
10
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
RBS1, 0 ← n
−
2
4
−
1
2
No Operation
IE ← 1 (Enable Interrupt)
−
2
6
−
IE ← 0 (Disable Interrupt)
2
6
−
2
6
Set HALT Mode
−
2
6
Set STOP Mode
Operation
) selected by the processor clock
CPU
Flag
Z AC CY
×
×
×
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