NEC mPD78F0730 Preliminary User's Manual page 273

Data hold registers
Request data registers
Peripheral control register
Figure 12-1 shows the block diagram.
INTUSB0B
INTUSB1B
INTUSB2B
INTRSUM
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CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
Table 12-1. Configuration of USB Function Controller USBF (2/2)
Item
UF0 EP0 read register (UF0E0R)
UF0 EP0 length register (UF0E0L)
UF0 EP0 setup register (UF0E0ST)
UF0 EP0 write register (UF0E0W)
UF0 bulk out 1 register (UF0BO1)
UF0 bulk out 1 length register (UF0BO1L)
UF0 bulk in 1 register (UF0BI1)
UF0 devise status register L (UF0DSTL)
UF0 EP0 status register L (UF0E0SL)
UF0 EP1 status register L (UF0E1SL)
UF0 EP2 status register L (UF0E2SL)
UF0 address register (UF0ADRS)
UF0 configuration register (UF0CNF)
UF0 interface 0 register (UF0IF0)
UF0 interface 1 to 4 registers (UF0IF1 to UF0IF4)
UF0 descriptor length register (UF0DSCL)
UF0 devise descriptor registers 0 to 17 (UF0DD0 to UF0DD17)
UF0 configuration/interface/endpoint descriptor registers 0 to 255 (UF0CIE0 to UF0CIE255)
USB function 0 buffer control register (UF0BC)
Figure 12-1. Block Diagram of USB Function Controller USBF
f
USB
(48 MHz)
Configuration
USB
Endpoint0R (64 bytes)
Endpoint0W (64 bytes)
Endpoint1
Endpoint2
SIE
Preliminary User's Manual U19014EJ1V0UD
Endpoint
(64 bytes × 2)
(64 bytes × 2)
I/O buffer
USB function 0 buffer
control register (UF0BC)
USBM
USBP
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