NEC mPD78F0730 Preliminary User's Manual page 91

(7) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTS.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 05H.
Address: FFA4H
Symbol
OSTS
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CHAPTER 5 CLOCK GENERATOR
Figure 5-8. Format of Oscillation Stabilization Time Select Register (OSTS)
After reset: 05H R/W
7 6
0 0
OSTS2 OSTS1 OSTS0
0 0
0 1
0 1
1 0
1 0
Other than above
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
2. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
3. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
4. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts ("a" below).
X1 pin voltage
waveform
Remark f : X1 clock oscillation frequency
X
Preliminary User's Manual U19014EJ1V0UD
5 4 3
0 0 0
Oscillation stabilization time selection
11
1 2 /f 170.7
X
13
0 2 /f 682.7
X
14
1 2 /f 1.37 ms
X
15
0 2 /f 2.73 ms
X
16
1 2 /f 5.46 ms
X
Setting prohibited
STOP mode release
a
2 1 0
OSTS2 OSTS1 OSTS0
f = 12 MHz f = 16 MHz
X X
µ µ
s 128 s
µ µ
s 512 s
1.024 ms
2.048 ms
4.096 ms
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