NEC mPD78F0730 Preliminary User's Manual page 353

Notes 1. This register can be cleared to 0 by the RESET signal because its write pointer, counter, and read
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CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
Table 12-8. Register Values in Specific Status (2/2)
Register Name
UF0E0R register
UF0E0L register
UF0E0ST register
UF0E0W register
UF0BO1 register
UF0BO1L register
UF0BI1 register
UF0DSTL register
UF0E0SL register
UF0E1SL register
UF0E2SL register
UF0ADRS register
UF0CNF register
UF0IF0 register
UF0IF1 register
UF0IF2 register
UF0IF3 register
UF0IF4 register
UF0DSCL register
UF0DDn register (n = 0 to 17)
UF0CIEn register (n = 0 to 255)
pointer are cleared to 0 when the RESET signal becomes active, in the same manner as clearing by the
UF0FICn register, as the register is controlled by FIFO.
2. This register cannot be cleared to 0. Because data can be written to it by FW, however, any value can
be written to the register (before doing so, however, be sure to set the EP0NKA bit of the UF0E0NA
register to 1).
After CPU Reset (RESET)
Note 1
Undefined
00H
00H
Note 1
Undefined
Note 1
Undefined
00H
Note 1
Undefined
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Note 2
Note 2
Preliminary User's Manual U19014EJ1V0UD
After Bus Reset
Value is held.
Value is held.
00H
Value is held.
Value is held.
Value is held.
Value is held.
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Value is held.
Note 2
Note 2
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