NEC mPD78F0730 Preliminary User's Manual page 302

(17) UF0 INT mask 1 register (UF0IM1)
This register controls masking of the interrupt sources indicated by the UF0IS1 register.
This register can be read or written in 8-bit units.
FW can mask occurrence of an interrupt request (INTUSB0B) from USBF by writing 1 to the corresponding bit
of this register.
UF0IM1
Bit position
6
5
4
3
2
1
0
302
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CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
7 6 4
5
0 E0INM E0
E0
INDTM ODTM
Bit name
E0INM This bit masks the EP0IN interrupt.
1: Mask
0: Do not mask (default value)
E0INDTM This bit masks the EP0INDT interrupt.
1: Mask
0: Do not mask (default value)
E0ODTM This bit masks the EP0OUTDT interrupt.
1: Mask
0: Do not mask (default value)
SUCESM This bit masks the Success interrupt.
1: Mask
0: Do not mask (default value)
STGM This bit masks the Stg interrupt.
1: Mask
0: Do not mask (default value)
PROTM This bit masks the Protect interrupt.
1: Mask
0: Do not mask (default value)
CPUDECM This bit masks the CPUDEC interrupt.
1: Mask
0: Do not mask (default value)
Preliminary User's Manual U19014EJ1V0UD
3 2 1
SUCESM STGM PROTM
Function
0
Address After reset
CPU FF38H 00H
DECM