NEC mPD78F0730 Preliminary User's Manual page 432

Figure 16-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
V
LVI
Supply voltage 2.7 V (TYP.)
(V )
DD
Note 1
1.8 V
V = 1.59 V (TYP.)
POC
0 V
Internal high-speed
oscillation clock (f )
RH
High-speed
system clock (f )
XH
(when X1 oscillation
is selected)
CPU
Internal reset signal
The operation guaranteed range is 1.8 V ≤ V
Notes 1.
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2. The internal high-speed oscillation clock and a high-speed system clock can be selected as the CPU
clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization
time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 17
LOW-VOLTAGE DETECTOR).
Remarks 1. V
2. V
3. For the
432
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CHAPTER 16 POWER-ON-CLEAR CIRCUIT
and Low-Voltage Detector
Set LVI to be
used for reset
Wait for oscillation
accuracy
stabilization
Starting oscillation is
specified by software.
Normal operation
(internal high-speed
oscillation clock)
Operation
stops
µ
Reset processing (20 s (TYP.))
: LVI detection voltage
LVI
: POC detection voltage
POC
µ
PD78F0730, be sure to set the 2.7 V/1.59 V POC mode by using the option byte
(POCMODE = 1).
Preliminary User's Manual U19014EJ1V0UD
Set LVI to be
used for interrupt
Wait for oscillation
accuracy
stabilization
Starting oscillation is
specified by software.
Reset period
Normal operation
(oscillation
(internal high-speed
stop)
Note 2 oscillation clock) Note 2
µ
Reset processing (20 s (TYP.))
≤ 5.5 V. To make the state at lower than 1.8 V reset
DD
Set LVI to be
used for reset
Wait for oscillation
accuracy
stabilization
Starting oscillation is
specified by software.
Reset period
Normal operation
(oscillation
(internal high-speed
stop) oscillation clock) Note 2
µ
Reset processing (20 s (TYP.))
Operation stops