NEC mPD78F0730 Preliminary User's Manual page 101

8-bit single-chip microcontroller
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<2> Setting the high-speed system clock as the main system clock (MCM register)
<3> Setting the main system clock as the CPU clock and selecting the division ratio (PCC register)
(4) Example of setting procedure when stopping the high-speed system clock
The high-speed system clock can be stopped in the following two ways.
• Executing the STOP instruction to set the STOP mode
• Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used)
(a) To execute a STOP instruction
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When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock
and peripheral hardware clock.
XSEL
MCM0
Selection of Main System Clock and Clock Supplied to Peripheral Hardware
1
1
High-speed system clock (f
Caution If the high-speed system clock is selected as the main system clock, a clock other than
the high-speed system clock cannot be set as the peripheral hardware clock.
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock
division ratio, use PCC0, PCC1, and PCC2.
CSS
PCC2
PCC1
0
0
0
0
0
1
Other than above
<1> Setting to stop peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 14 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after standby release
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation
is stopped (the input of the external clock is disabled).
CHAPTER 5 CLOCK GENERATOR
Main System Clock (f
)
XP
)
XH
PCC0
0
0
f
XP
0
1
f
/2 (default)
XP
2
1
0
f
/2
XP
3
1
1
f
/2
XP
4
0
0
f
/2
XP
Setting prohibited
Preliminary User's Manual U19014EJ1V0UD
Peripheral Hardware Clock (f
PRS
High-speed system clock (f
)
XH
CPU Clock (f
) Selection
CPU
)
101

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