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(21) UF0 INT clear 0 register (UF0IC0)
This register controls clearing the interrupt sources indicated by the UF0IS0 register.
This register is write-only, in 8-bit units. If this register is read, the value FFH is read.
FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is
automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a
bit of this register automatically sets the bit to 1. Writing 1 is invalid.
BUS
UF0IC0
RSTC
Bit position
7
6
2
1
0
306
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CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
7
6
5
4
1
RSU
1
SPDC
Bit name
BUSRSTC
This bit clears the Bus Reset interrupt.
0: Clear
RSUSPDC
This bit clears the Resume/Suspend interrupt.
0: Clear
SETRQC
This bit clears the SET_RQ interrupt.
0: Clear
CLRRQC
This bit clears the CLR_RQ interrupt.
0: Clear
EPHALTC
This bit clears the EP_Halt interrupt.
0: Clear
Preliminary User's Manual U19014EJ1V0UD
3
2
1
0
1
SET
CLR
EP
RQC
RQC
HALTC
Function
Address
After reset
FF4AH
FFH
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