NEC mPD78F0730 Preliminary User's Manual page 477

Instruction
Group
8-bit
operation
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
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Mnemonic Operands
SUB A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
SUBC A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
AND A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 21 INSTRUCTION SET
Clocks
Bytes
Note 1 Note 2
− A, CY ← A − byte
2 4
(saddr), CY ← (saddr) − byte
3 6 8
− A, CY ← A − r
Note 3
2 4
− r, CY ← r − A
2 4
A, CY ← A − (saddr)
2 4 5
A, CY ← A − (addr16)
3 8 9
A, CY ← A − (HL)
1 4 5
A, CY ← A − (HL + byte)
2 8 9
A, CY ← A − (HL + B)
2 8 9
A, CY ← A − (HL + C)
2 8 9
− A, CY ← A − byte − CY
2 4
(saddr), CY ← (saddr) − byte − CY
3 6 8
− A, CY ← A − r − CY
Note 3
2 4
− r, CY ← r − A − CY
2 4
A, CY ← A − (saddr) − CY
2 4 5
A, CY ← A − (addr16) − CY
3 8 9
A, CY ← A − (HL) − CY
1 4 5
A, CY ← A − (HL + byte) − CY
2 8 9
A, CY ← A − (HL + B) − CY
2 8 9
A, CY ← A − (HL + C) − CY
2 8 9
− A ← A ∧ byte
2 4
(saddr) ← (saddr) ∧ byte
3 6 8
− A ← A ∧ r
Note 3
2 4
− r ← r ∧ A
2 4
A ← A ∧ (saddr)
2 4 5
A ← A ∧ (addr16)
3 8 9
A ← A ∧ (HL)
1 4 5
A ← A ∧ (HL + byte)
2 8 9
A ← A ∧ (HL + B)
2 8 9
A ← A ∧ (HL + C)
2 8 9
Preliminary User's Manual U19014EJ1V0UD
Operation
) selected by the processor clock
CPU
Flag
Z AC CY
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477