Operation List - NEC mPD78F0730 Preliminary User's Manual

21.2 Operation List

Instruction
Group
8-bit data
transfer
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
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Mnemonic Operands
MOV r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
XCH A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 21 INSTRUCTION SET
Clocks
Bytes
Note 1 Note 2
− r ← byte
2 4
(saddr) ← byte
3 6 7
− sfr ← byte
3 7
− A ← r
Note 3
1 2
− r ← A
Note 3
1 2
A ← (saddr)
2 4 5
(saddr) ← A
2 4 5
− A ← sfr
2 5
− sfr ← A
2 5
A ← (addr16)
3 8 9
(addr16) ← A
3 8 9
− PSW ← byte
3 7
− A ← PSW
2 5
− PSW ← A
2 5
A ← (DE)
1 4 5
(DE) ← A
1 4 5
A ← (HL)
1 4 5
(HL) ← A
1 4 5
A ← (HL + byte)
2 8 9
(HL + byte) ← A
2 8 9
A ← (HL + B)
1 6 7
(HL + B) ← A
1 6 7
A ← (HL + C)
1 6 7
(HL + C) ← A
1 6 7
− A ↔ r
Note 3
1 2
A ↔ (saddr)
2 4 6
− A ↔ (sfr)
2 6
A ↔ (addr16)
3 8 10
A ↔ (DE)
1 4 6
A ↔ (HL)
1 4 6
A ↔ (HL + byte)
2 8 10
A ↔ (HL + B)
2 8 10
A ↔ (HL + C)
2 8 10
Preliminary User's Manual U19014EJ1V0UD
Operation
) selected by the processor clock
CPU
Flag
Z AC CY
× × ×
× × ×
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