NEC mPD78F0730 Preliminary User's Manual page 418

Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
2. Even if "internal low-speed oscillator can be stopped by software" is selected by the option
byte, the internal low-speed oscillation clock continues in the STOP mode in the status before
the STOP mode is set. To stop the internal low-speed oscillator's oscillation in the STOP mode,
stop it by software and then execute the STOP instruction.
3. If the STOP instruction is executed with AMPH set to 1 when the internal high-speed oscillation
clock or external main system clock is used as the CPU clock, the internal high-speed
oscillation clock or external main system clock is supplied to the CPU 5
mode has been released.
(2) STOP mode release
High-speed system
clock (X1 oscillation)
Internal high-speed
oscillation clock
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
Note When AMPH = 1
The STOP mode can be released by the following two sources.
418
Downloaded from Elcodis.com electronic components distributor
CHAPTER 14 STANDBY FUNCTION
Figure 14-5. Operation Timing When STOP Mode Is Released
STOP mode release
STOP mode
Wait for oscillation
accuracy
stabilization
HALT status
(oscillation stabilization time set by OSTS)
µ
Note
5 s (TYP.)
Preliminary User's Manual U19014EJ1V0UD
Automatic selection
Internal high-speed
oscillation clock
Clock switched
by software
µ
s (MIN.) after the STOP
High-speed system clock
High-speed system clock