Compiling And Testing The Design In Hardware - Intel F-Tile SDI II Agilex User Manual

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1. F-Tile SDI II Intel Agilex
710496 | 2022.01.28

1.4. Compiling and Testing the Design in Hardware

Figure 8. Compiling and Testing the Design Flow
Compile Design
in Quartus Prime
To compile and run a demonstration test on the hardware design example, follow
these steps:
1. Open the Intel Quartus Prime project (
Quartus directory.
2. To perform Intel Quartus Prime compilation, click Processing
Compilation.
3. Connects the Nextera SDI daughter card to FMC port A on the development kit.
4. For parallel loopback design, connects the BNC RX connector (J1/12G In) to an
external video source and connects the TX connector (J2/12G Out) to a video
analyzer. For serial loopback design, connects the BNC TX connector (J2/12G
Out) to RX connector (J1/12G In) or a video analyzer.
5. Ensure all the switches on the development kit are in their default position per
Agilex I-series SoC Development Kit User Guide.
6. After the compilation completes, open Programmer and program the
generated
7. For serial loopback design, you need to open System Console to control the
internal video pattern generator.
a. Go to Tools
b. After the initialization, type
pattern generator control UI.
c. Select your desired video format through the UI.
Note: To allow segmented frame video format (1080sF30, 1080sF25) and
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FPGA IP Design Example Quick Start Guide
Set Up Hardware
Software
file to the development kit.
.sof
System Debugging Tools and click System Console.
interlaced video format (1080i60, 1080i50) to be correctly differentiated in
external analyzer, you must insert Payload ID in the serial loopback design
Program Device
sdi_ii_agi_demo.qpf
source ../hwtest/tpg_ctrl.tcl
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F-Tile SDI II Intel Agilex
Test Design
in Hardware
) located in
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FPGA IP Design Example User Guide
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