Intel F-Tile SDI II Agilex User Manual page 20

Table 6. Device Under Test (DUT) Components
Component
SDI II
F-tile PMA/FEC Direct PHY
PHY adapter
Table 7. Loopback Top Components
Component
Loopback FIFO
Table 8. Video Pattern Generator Components
Component
Video Pattern Generator
Pattern Gen Control PIO
JTAG to Avalon Master Bridge
Table 9. Common Blocks at Top Level
Common Block
Reference and System PLL Clocks
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
20
• TX
— The IP core receives the video data from top level and encodes the
necessary information, for example line number, CRC or payload ID into
the data streams.
• RX
— The IP core receives the parallel data from Transceiver Native PHY and
performs necessary decoding, such as descrambling, realigning the data
and extracting the necessary information.
— The output data from these blocks connects to the SDI F-tile PHY adapter
module before passing it to Direct PHY IP.
• TX
— Hard transceiver block which receives the parallel data from SDI core and
serialize the data before transmitting it.
• RX
— Hard transceiver block to receive the serial data from an external video
source.The PHY runs in System PLL clocking mode and system clock
output always runs at a higher clock frequency than the native PMA
recovered clock.
SDI mode
HD-SDI single rate
3G-SDI single rate
12G-SDI single rate
Adapter block which includes DCFIFO for converting the bit width of parallel data
between transceiver and SDI core, as well as to transfer the data between these
two clock domains.
This module contains DCFIFO for video data transferring between receiver clock
domain and transmitter clock domain.
Basic video pattern generator which can support SD-SDI up to 12G-SDI video
formats with 4:2:2 YCbCr. You can select static video with colorbar pattern or
pathological pattern from this pattern generator.
Provides a memory-mapped interface for controlling the video pattern generator.
Provides System Console host access to the Parallel I/O (PIO) IP in the design
via the JTAG interface.
This IP connects the System PLL output clock as well as the TX PLL and RX CDR
reference clock to the F-tile PMA/FEC Direct PHY IP.
System PLL clock output is always set to run at a higher clock frequency than the
native PMA recovered clock.
2. Design Example Detailed Description
710496 | 2022.01.28
Description
Minimum System PLL output
frequency
150 MHz
300 MHz
600 MHz
Description
Description
Description
continued...
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