Intel F-Tile SDI II Agilex User Manual page 37

2. Design Example Detailed Description
710496 | 2022.01.28
Signal names
dout_b
dout_valid_b
trs_b
ln_b
vpid_byte1
vpid_byte2
vpid_byte3
vpid_byte4
vpid_byte1_b
vpid_byte2_b
vpid_byte3_b
vpid_byte4_b
line_f0
line_f1
Table 21. Pattern Generator control module signals
Signal name
avmm_clk_in_clk
tx_clkout_in_clk
avmm_clk_reset_n
pattgen_rst_reset_in
0
pattgen_rst_reset_in
1
pattgen_rst_reset_ou
t
pattgen_ctrl_pio_out
_port
Send Feedback
Direction Width
Output 20
Output 1
Output 1
Output 11*N
Output 8*N
Output 8*N
Output 8*N
Output 8*N
Output 8*N
Output 8*N
Output 8*N
Output 8*N
Output 11*N
Output 11*N
Direction Width
Input 1
Input 1
Input 1
Input 1
Input 1
Input 1
Output 12
Description
Data output signal for link B (HD dual-link).
Data valid output signal for link B (HD dual-link).
TRS output signal for link B (HD dual-link).
Line number output signal to be connected to
sdi_tx_ln_b input signal on TX/Du top.
Payload ID output signal to be connected to
sdi_tx_vpid_byte1 input signal on TX/Du top.
Payload ID output signal to be connected to
sdi_tx_vpid_byte2 input signal on TX/Du top.
Payload ID output signal to be connected to
sdi_tx_vpid_byte3 input signal on TX/Du top.
Payload ID output signal to be connected to
sdi_tx_vpid_byte4 input signal on TX/Du top.
Payload ID output signal to be connected to
sdi_tx_vpid_byte1_b input signal on TX/Du top.
Payload ID output signal to be connected to
sdi_tx_vpid_byte2_b input signal on TX/Du top.
Payload ID output signal to be connected to
sdi_tx_vpid_byte3_b input signal on TX/Du top.
Payload ID output signal to be connected to
sdi_tx_vpid_byte4_b input signal on TX/Du top.
Line number output signal to be inserted with Payload
ID. This signal must be connected to sdi_tx_line_f0 input
signal on TX/Du top.
Line number output signal to be inserted with Payload
ID. This signal must be connected to sdi_tx_line_f1 input
signal on TX/Du top.
Description
Clock signal to AVMM interface.
Clock signal to Parallel I/O (PIO) IP. This clock must
share the same clock as video pattern generator.
Reset signal to AVMM interface.
Input reset signals to a reset synchronizer which
synchronize the reset to tx_clkout_in_clk clock domain.
Output reset from reset synchronizer. This reset is
synchronized to tx_clkout_in_clk clock domain and
connected to video pattern generator's input reset.
Output control signal from PIO to control video pattern
generator.
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F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
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